Abstract. A contact hole shrink process using directed self-assembly lithography (DSAL) for sub-30 nm contact hole patterning is reported on. DSAL using graphoepitaxy and poly (styrene-block-methyl methacrylate) (PS-b-PMMA) a block copolymer (BCP) was demonstrated and characteristics of our process are spin-on-carbon prepattern and wet development. Feasibility of DSAL for semiconductor device manufacturing was investigated in terms of DSAL process window. Wet development process was optimized first; then critical dimension (CD) tolerance of prepattern was evaluated from three different aspects, which are DSA hole CD, contact edge roughness (CER), and hole open yield. Within 70 þ ∕ − 5 nm hole prepattern CD, 99.3% hole open yield was obtained and CD tolerance was 10 nm. Matching between polymer size and prepattern size is critical, because thick PS residual layer appears at the hole bottom when the prepattern holes are too small or too large and results in missing holes after pattern transfer. We verified the DSAL process on a 300-mm wafer at target prepattern CD and succeeded in patterning sub-30 nm holes on center, middle, and edge of wafer. Average prepattern CD of 72 nm could be shrunk uniformly to DSA hole pattern of 28.5 nm. By the DSAL process, CD uniformity was greatly improved from 7.6 to 1.4 nm, and CER was also improved from 3.9 to 0.73 nm. Those values represent typical DSAL rectification characteristics and are significant for semiconductor manufacturing. It is clearly demonstrated that the contact hole shrink using DSAL is a promising patterning method for next-generation lithography.

No abstract

No abstract

No abstract

No abstract

No abstract

In this study, we conducted electrical via chain yield tests for the purpose of verifying the total process performance of directed self-assembly (DSA) contact hole shrink process. DSA was utilized on the via level connecting between two metal levels. From the analysis of single via resistance data, the best process condition was determined and the via chain yield was obtained. The best yield was 74% at the via chain size of 2.3k and one chip passed the test at the via chain size of 358k. In order to find the root cause of the via chain yield degradation, the failure location was identified by absorbed electron current images and STEM images were taken. It was found that the via did not contact the lower metal level at the failure location. However, we concluded that it was not necessarily caused by DSA process because such failure mode was also observed for the via chains without DSA. Although the via chain size tested at the pre-production stage is much larger by orders of magnitude than the via chain size tested in this study, we believe that significant progress has been made in this study toward semiconductor device manufacturing using DSA contact hole shrink process.

We summarize the metrology and inspection required for the development of nanoimprint lithography (NIL) and directed self-assembly (DSA), which are recognized as candidates for next generation lithography. For NIL, template inspection and residual layer thickness (RLT) metrology are discussed. An optical-based inspection tool for replica template inspection showed sensitivity for defects below 10 nm with sufficient throughput. Scatterometry was applied for RLT metrology. Feedback control with scatterometry improved RLT uniformity across an imprinting field. For DSA, metrology for image placement and cross-sectional profile are addressed. Design-based scanning electron microscope (SEM) metrology utilizing a die-to-database electron beam (EB) inspection tool was effective for image placement metrology. For the cross-sectional profile, a holistic approach combining scatterometry and critical dimension SEM was developed. The technologies discussed here will be important when NIL and DSA are applied for IC manufacturing, as well as in the development phases of those lithography technologies.