A field trial of 100-Gbit/s Ethernet over an optical transport network (OTN) is conducted using a real-time digital coherent signal processor. Error free operation with the Q-margin of 3.2 dB is confirmed at a 100 Gbit/s Ethernet analyzer by concatenating a low-density parity-check code with a OTN framer forward error correction, after 80-ch WDM transmission through 6 spans x 70 km of dispersion shifted fiber without inline-dispersion compensation. Also, the recovery time of 12 msec is observed in an optical route switching experiment, which is achieved through fast chromatic dispersion estimation functionality.

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In high-speed data link systems of over 40Gb/s, the data decision point in the CDR circuit is not often the optimum position of the eye diagram. For example, asymmetrical waveform distortion, internal delay mismatch, or internal voltage offset causes the misalignment of the decision point in the vertical and/or horizontal directions. Furthermore, this misalignment sometimes rapidly and randomly varies over time. To overcome a severe degradation of BER performance due to this misalignment, a 40Gb/s CDR circuit integrated with an adaptive decision-point control scheme by using an eye-opening monitor [1-3] feedback is developed. The key approaches are follows: 1) a 40Gb/s high-precision eye-opening monitor (EOM) circuit to detect an optimum decision point, 2) an adaptive decision-point control (ADPC) scheme by using the EOM feedback, 3) a decisionpoint adjustable self-aligned phase detector to achieve the ADPC operation. The combination of these approaches improves both the BER performance and the stability of CDR operation. Figure 11.5.1 shows the adaptive decision-point control CDR architecture and the EOM concept. This CDR has not only a main CDR feedback loop but also an ADPC feedback loop. The main CDR loop includes the decision-point adjustable self-aligned phase detector with a double-edge-triggered decision (DETDEC) circuit. On the other hand, the ADPC loop includes the EOM circuit, which consists of an additional monitor decision (DEC) circuit, an XOR gate, and a LPF. The decision point of the monitor DEC can be independently controlled in both the vertical and horizontal directions and used to two-dimensionally scan the input waveform. By using the XOR gate, a code mismatching can be found between both the main and monitor decision results, which is defined as a code-mismatch error rate (CMER). As a result of the CMER from 2-D scanning, the eye-opening area and the current position of the main decision point can be found. To simplify the circuits, the LPF is used to obtain the analog voltage that corresponds to the CMER, instead of counting the output pulses in the XOR gate. An off-chip PC-based algorithm is used to control the monitor decision point and calculate the 2-D eye-opening map and the optimum decision point. Since the shape of the eye-opening strongly correlated with the BER performance, an optimum position of the decision-point can be estimated based on the shape of the eye-opening. In this work, the position with a maximum eye-opening margin in both the vertical and horizontal directions is defined as the optimum position. Finally, the main decision point is adjusted by using calculated optimum decisionpoint feedback. Furthermore, because the EOM and ADPC flows can be run independently to the main CDR loop, the data decision point in the CDR can be continuously optimized by running the EOM and ADPC at regular time intervals. Although this feedback now takes several seconds due to the PC-based algorithm, an on-chip algorithm can reduce the feedback response time in the order of milliseconds. Th...

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