We present enhanced 90 nm node CMOS devices on a partially depleted SO1 with 40 M I gate length, featuring advanced process modules for manufacture including RSD (Raised SourceDrain), disposable spacer, final spacer for SiD doping and silicide proximity, NiSi, and thermally optimized MOL (Middle-of-Line) process. For the first time, we systematically designed silicide proximity in SO1 and post-activation thermal cycles to improve series resistance and gate activation. This paper demonstrates decoupled effects of the individual performance boosters on drive currents and minimization of dopant deactivation, which resulted in dramatic improvement of drive currents by 11% to 19% (820 @/um and 420 W u m at Ioff = 40 nNum with Vdd = l.OV, for NFET and P E T , respectively), significant reduction in effective gate oxide thickness under gate inversion by -1.2 A and -2.1 A, for NFET and PFET, respectively, and an excellent inverter delay of less than 5.4 ps at Lgate of 40 nm.
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