This article provides a detailed study of performance and reliability issues and trade-offs in silicon carbide (SiC) power MOSFETs. The reliability issues such as threshold voltage variation across devices from the same vendor, instability of threshold voltage under positive and negative gate bias, long-term reliability of gate oxide, screening of devices with extrinsic defects by means of gate voltage, body diode degradation, and short circuit withstand time are investigated through testing of commercial devices from different vendors and two-dimensional simulations. Price roadmap and foundry models of SiC MOSFETs are discussed. Future development of mixed-mode CMOS circuits with high voltage lateral MOSFETs along with 4−6× higher power handling capability compared to silicon circuits has been described.
650 V SiC planar MOSFETs with various JFET widths, JFET doping concentrations, and gate oxide thicknesses were fabricated by a commercial SiC foundry on two six-inch SiC epitaxial wafers. An orthogonal P+ layout was used for the 650 V SiC MOSFETs to reduce the ON-resistance. The devices were packaged into open-cavity TO-247 packages for evaluation. Trade-off analysis of the static and dynamic performance of the 650 V SiC power MOSFETs was conducted. The measurement results show that a short JFET region with an enhanced JFET doping concentration reduces specific ON-resistance (Ron,sp) and lowers the gate-drain capacitance (Cgd). It was experimentally shown that a thinner gate oxide further reduces Ron,sp, although with a penalty in terms of increased Cgd. A design with 0.5 μm half JFET width, enhanced JFET doping concentration of 5.5×1016 cm−3, and thin gate oxide produces an excellent high-frequency figure of merit (HF-FOM) among recently published studies on 650 V SiC devices.
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