An efficient interconnects modeling and optimization methodology is proposed for multi-GHz clock network design. High frequency effects, including inductance and proximity effects are captured. The results are validated through comparisons with electromagnetic simulations and measured data taken from a Cu/SiO 2 90nm process test chip.
Topologies comparison of a IGHz quadrature voltage convolled oscillator, VCO. based on simulation results is presented. VCO circuits are simulated using 0.25micron CMOS process from 2 . W supply. The comparison is introduced from two different perspectives: constant VCO DC power and constant output swing. The main differences between different topologies seekng same targeted VCO specifications are shown.
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