RLC parasitic extraction and circuit model optimization for Cu/SiO/sub 2/-90nm inductance structures

Abstract

An efficient interconnects modeling and optimization methodology is proposed for multi-GHz clock network design. High frequency effects, including inductance and proximity effects are captured. The results are validated through comparisons with electromagnetic simulations and measured data taken from a Cu/SiO 2 90nm process test chip.

High-frequency interconnect modeling for global signal networks

“…After determining γ and Z0, the values for R, L, and C can be directly obtained from: 9-11 [7], [10].…”

“…In order to take into consideration the effects that become apparent at high frequencies, the works in [3], [6], [7] present a modeling approach based on S-parameter measurements. In these case works, the values for R l , L l , and C l are obtained from the characteristic impedance Z0 and the propagation constant γ of the interconnection, which are determined from S-parameter measurements.…”

“…In this work, we obtain and analyze the transmission line model for global interconnections using: a) basic mathematical expressions and technology parameters [2], [4], [5]; and b) from S-parameter simulations [3], [6], [7]. Then, the model is used to show the accurate prediction of the delay associated with long interconnection lines.…”