Cu 2 WSe 4 nanosheets were synthesized by hot-injection method and employed as interfacial layers between the p-Si and Au metal via spin coating technique. The capacitance-voltage (C-V) and conductance-voltage (G-V) measurements were performed on the Cu 2 WSe 4 /p-Si heterojunction device depending on wide range temperatures from 80 to 400 K by 40 K steps. The device exhibited decreasing capacitance behavior with increasing temperature at the inversion region because of the interface states and series resistance. The conductance values increased with increasing temperature owing to increasing free charge carriers. The series resistance (R s ) and interface states density (N ss ) were extracted from C-V and G-V measurements and discussed in the details. The results highlighted that the electrical parameters are a strong function of the voltage and temperature. The Au/Cu 2 WSe 4 /p-Si device can be employed for controllable capacitor applications.

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The R factors employed in crystal structure analysis can also be used in connection with clay minerals to determine the amount of defects whose types are already known. For this purpose, using the unit-cell parameters of kaolinite with identical layers, (02,11) and (20,13) diffraction bands were calculated on the basis of a variable parameter model containing only +b/3 translational stacking faults. The parameters of the model were varied to obtain the best fit between the calculated and observed patterns with respect to both intensity and profile. Three different R factors were used as a criterion for the best fit and the parameters yielding the smallest R value were accepted as describing the actual structure. In addition, a linear regression analysis is performed between observed and calculated intensities to determine the quality of the fit. Correlation coefficients, obtained from this analysis, are used as an indication of the effectiveness of corresponding R factors.

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