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Error control coding is essential for semiconductor memory systems used in the space radiation environment because memory chips in this environment often suffer from single event upsets (SEUs). This paper presents the development of encoders and decoders of error control codes suitable for the space radiation environment. To select suitable error control codes, we analyze error patterns and error counts in in-flight data of a solid state recorder installed in the Mission Demonstration test Satellite-1 (MDS-1). Based on this analysis, six classes of linear error control codes are selected, and encoders and decoders of these codes are designed and implemented using an FPGA. To reduce the decoding delay, the decoders are designed based on a parallel decoding method. Evaluation of the implemented FPGA shows that the decoders have 45K to 300K gates with decoding delay of about 20 ns.

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