An efficient and cost-effective power converter is a pre-requisite for the modern power applications. With the evolvement of matured medium power self-commutated switching devices, multilevel inverters (MLIs) are emerged as a promising solution for high-power medium-voltage applications. Though, MLIs are performing a promising role in industrial applications, their high device count, size, cost and control complexity have restricted their market penetration. To address the disadvantages of MLIs, researchers are continuously contributing to new generation topologies under the name of reduced switch count (RSC) MLIs. From the past decade, numerous RSC-MLIs topologies have been reported for various applications. Therefore, this paper presents a comprehensive review and classification of RSC-MLI topologies, in terms of their structure, features, limitations, suitability and selection for specific applications..

In recent times, reduced switch count multilevel inverter (RSC-MLI) has become an emerging area of research in power electronic converters. To control these RSC-MLI topologies, various novel modulation schemes are reported. Multireference is one of such modulation scheme reported for various RSC topologies, such as T-type. However, the performance of this conventional scheme results in high total harmonic distortion (THD) in line voltages, when compared with the conventional level shifted pulse-width modulation scheme. This observation is clearly presented in this study and the reason for its degraded THD performance has been deeply discussed. To alleviate this problem, a modified multi-reference dual-carrier modulation technique with multiple references and two carriers is proposed. To implement this proposed modulation technique, an alternate carrier and modulation signals arrangement with multiple carriers and single reference is also presented. Finally, a comparative THD performance of the proposed and conventional modulation schemes is carried out on a five-level T-type MLI and obtained simulation results are validated experimentally.

The significant reduction in switch count of symmetrical/asymmetrical reduced switch count multilevel inverters (RSC-MLI) topologies has modified the operation of inverter such that the conventional carrier-based pulse width modulation (PWM) schemes such as level-shifted PWM and phase-shifted PWM can no more realise them. To control these RSC-MLI topologies, reduced carrier PWM schemes with modified switching logic gained more prominence. These schemes involve suitable logical expressions to realise the switching states of the inverter. However, these logical expressions vary with topological arrangement and number of levels. Moreover, these schemes produce high total harmonic distortion (THD) in line-voltages. Therefore, to improve the line-voltage THD and generalise the switching logic, a modified reduced carrier PWM scheme with unified logical expressions is presented here. The proposed PWM scheme is directly valid for any topology and can be easily scalable to any number of levels in the inverters. To validate the implementation of the proposed PWM to control any RSC-MLI, experimental studies of various asymmetrical RSC-MLI topologies with the proposed PWM scheme are carried out. Further, to verify the superiority of the proposed scheme in terms of THD, complexity, scalability, and computation burden, its performance is compared with carrier-based PWM schemes reported in the literature.

Neutral shifting (NS) is a popular scheme to achieve fault tolerance operation (FTO) of multilevel inverters (MLIs) such as cascaded H-bridge (CHB). This fault tolerance scheme (FTS) can be realised with/without zero-sequence voltage injection. Among these, NS with zero-sequence injection FTS is relatively easier to implement. However, this scheme is not generalised for multiple open-circuit faults. Moreover, NS-FTS schemes are not directly applicable for fault tolerance of reduced switch count (RSC)-MLIs, as these inverters have limited redundancies. Therefore in this study, FTO for RSC-based multilevel dc-link (MLDCL) inverter using NS zero-sequence injection FTS is proposed for simultaneous failure of multiple switch faults. Generalised mathematical equations are derived to calculate the magnitude and phase angle of injected zero-sequence voltage for obtaining balanced line voltages with uniform power sharing among all healthy units. The proposed generalised NS-FTS with zero-sequence injection is implemented on three-phase 15-level MLDCL inverter for various fault conditions. The obtained simulation results are validated experimentally on nine-level MLDCL inverter.

The reduced switch count multilevel inverter (RSC‐MLI) is the latest trend in power electronic converters due to reduction in the switch count and cost. However, a large number of RSC‐MLIs have not yet reached to the application level because of the absence of modularity, unequal load‐sharing among DC sources and the absence of switching redundancies. On the other hand, multilevel dc‐link (MLDCL) and switched series parallel sources (SSPS) RSC‐MLI topologies are modular structures with adequate switching redundancies and can be an alternative to conventional cascaded H‐bridge (CHB) for grid‐connected photovoltaic (PV) systems. Therefore, in this paper, a comprehensive comparison among CHB, MLDCL and SSPS topologies has been carried out for grid connected PV application. Based on the outcome, an asymmetric 11 kV three‐phase 11‐level SSPS RSC‐MLI is chosen. In this combination, a common non‐linear sliding mode controller (SMC) is developed for generating maximum PV power from asymmetric single‐stage PV sources by linearizing the non‐linear PV system using an effective feedback linearization scheme. The PV power extracted is delivered to the grid by controlling SSPS RSC‐MLI using another SMC. The performance of the system under wide variations of insolation levels is verified in MATLAB and further validated in hardware‐in‐the‐loop OPAL‐RT controller.

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Advancement of power electronics and fabrication of self-commutated switching devices enhanced the prominence of multilevel inverters (MLI) for high power applications. The ability of MLI to be implemented with matured medium power electronic devices and less dc-link voltagesturnedtobeaviablealternativefor bulky transformer-based powerconverterforhigh-powermedium-voltageapplications. Though, these converters have wide market penetration for input transformer-less applications, their increase in switch count for higher-levels imposed size cost and complexity limitationsand, restricted them to lower levels.Need to reduce the device count requirement of the classical MLI configurations lead to the development of Reduced Device count (RDC) MLI configurations. Among the various RDC topologies reported, T-type has most appreciable reduced in switch count. This paper presents the implementation of the cascaded T-type RDC-MLI. Further the closed performance of the considered nine-level Cascaded T-type configuration is investigated by developing a shunt active power filter. The efficacy of the inverter for power quality enhancement is demonstrated in MATLAB/Simulinkenvironment.

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