This paper describes a new concept for low power consumption TFT-LCDs, based on monolithic multi-drivers. The multi-driver architecture consists of two data line drivers, one analogue, one binary, that can operate in tandem or independently. The analogue driver allows the display to show high quality full colour video images. The binary driver provides 8 colour text data display, either on its own, or superimposed onto the image provided by the analogue driver. Operation of the binary driver consumes 1/10 th of the power that operation of the analogue driver needs. The display module can therefore operate at substantially lower power for many display applications, yet still achieve high display performance when demanded.
This paper describes an advanced digital display that we have developed for future mobile applications. The 2" QVGA LCD display contains multi-format digital drivers integrated with a low-temperature Continuous Grain Silicon TFT process. These drivers automatically configure the display format based on the contents of the image data that is transmitted to the panel. This strategy provides an optimum balance between display performance and power consumption.
A key requirement for the development of advanced digital drivers for Low Temperature Poly-Silicon (LTPS) active matrix displays is the provision of a high bandwidth, high resolution Digital to Analogue Converter (DAC) as a prerequisite for higher level integration. For a given panel specification and data rate, the bandwidth and resolution of the conversion process directly influence the efficiency of a digital driver implementation in terms of bezel size, transistor count and power consumption. This paper is concerned with the design and realization of a programmable high performance DAC architecture which meets the requirements for a compact and highly efficient digital data driver. The high performance of the two-stage architecture is achieved by means of a novel pre-charge arrangement that not only increases the speed of operation, but also provides for offset compensation of an analogue buffer with considerably reduced slew rate requirements and power consumption. A switched capacitor implementation of the DAC architecture is presented and the theoretical specifications are verified by simulation. The application of the new architecture to advanced digital drivers with programmable input data resolution is briefly discussed.
HDR 2D‐backlight designs and some process for each of automotive/monitor, mobile device, and future Reality applications are presented. On‐chip lens and confining wall reflector structure are suitable for automotive/monitor applications, and 5,000nits of peak brightness will be performed in real usage. The white LED chip architecture is proposed for mobile applications of 2‐1mm thin backlight. The power efficiency is evaluated to be almost double, and the 500lux ambient light contrast is 5 times larger than a 15.6‐inch OLED display. The 0.5mm thin film backlight with micro‐LED chips for Reality applications is proposed.
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