No abstract

This article presents a numerical and experimental investigation for the single-phase forced laminar convective heat transfer through arrays of microchannels in micro heat exchangers to be used for cooling power-intensive semiconductor packages, especially the stacked multi-chip modules (MCMs). In the numerical analysis, a parametric study was carried out for the factors affecting the efficiency of heat transfer in the flow of coolants through parallel rectangular microchannels. In the experimental study, the cooling performance of the micro heat exchanger was tested on the prototypes of stacked MCMs with different channel dimensions. The simulation result and the experiment data were acceptably accordant within a wide range of design variations, suggesting the numerical procedure as a useful method for designing the cooling mechanism in stacked multichip packages and similar electronic applications.

No abstract

In the semiconductor industry, the memory device has not been considered as a high power consuming product. However, the increase in the market requirements for high speed and high density has resulted in memory devices that consume more power.Especially, a memory module accommodated with many high speed memory devices can reach to very high levels of power consumption, which in turn, can reach to very high junction temperatures. Therefore, the devices can not be operated properly without thermal management. Hence, in this paper, we are looking for a way to manage the heat generated in a high power memory module. To achieve this goal, a plate fin type heat sink based on air cooling was adopted with consideration of constraints related to the implementation of its thermal solutions. Then, the cooling capability of the memory module was estimated by a parametric study. The parametric study shows that a 20mm module pitch is necessary to dissipate the amount of heat that is targeted in this paper, which is 30W. With the 20mm module pitch, an optimized heat sink configuration was designed by simulation and the cooling performance of the designed heat sink was validated by experiments. For the experiment, test modules were assembled and the junction temperatures of memory devices mounted on modules was measured on a test board. The results showed that simulated and measured data well correlate with each other within acceptable ranges. The maximum cooling capability of the designed heat sink is 37.1W with a 20mm module pitch.

Single column transient isotachophoresis (TITP) system and cyclic CE chip is integrated on PDMS (polydimethylsiloxane) chip. ITP part can concentrate low concentrated sample by over the 500-folded times. In addition, as additional coating of EOF modifier, the velocity and resolution is improved. The focusing of sample and separation is processed in a single column. The TITP chip has the disadvantage of low resolution, because it has the limited channel length with a limited voltage for a general CE chip. So, the focused sample was separated in the cyclic CE. The focused high concentration sample became the plug of the cyclic CE. Cyclic CE, which is the one of the channel network structures, has advantages in downsizing and a low operation voltage. However, there are some problems such as sample loss when the injected plug encounters the junctions in the middle of the channel. This paper will show the optimum design that these problem was considered. By a dyestuff experiment, the procedure of focusing step and separation are observed and studied. All these procedure is operated by just E-field. The chloride ion is used as the leading electrolyte, and the volume of injection is about 20 pL. Under our LIF conditions, the sample concentrated over the 500-folded times and cyclic CE chip showed < 2 % degradation per junction. This means the high resolution CE analysis has 100,000 plate numbers after a three and one quarter cycle in just 3.5 x 6 cm chip.

No abstract

No abstract

No abstract