In microwave power transistors one of the most serious short-term failure modes is due to what is known ae "Current-Hogging" effect. The emitter ballasting is the most effective way of minimizing this problem and is being pract,iced widely today.However, since the exact account of this effect requires a complex three dimensional thermal analysis coupled with min0rit.y carrier injection mechanism, which in turn is dependent on the external circuit, complete analysis of this phenomenon has not been carried out thus far.We have obtained a Green's function for the temperature in a three dimensional silicon dice and obtained the local junction temperatures of a mu!ti-fingered power transistor corresponding to reasonable initializing emitter current values.The emitter currents were then recalculated using these temperature values for net junction voltages equal to the applied emitter-base voltage minus IERE drops.This iteration scheme was continued until self-consistent current and temperature distribution were obtained.The current and temperature distribution were calculated for one section of a prototype power transistor with fhrax in excess of 16 GHZ and capable of 1.3 watt class C power with 9 dB gain a t 4 GHZ. Excellent agreements have been obtained between the calculated and measured values. 4.4Several new designs of microwave power transistors have been reported in the past few years. However, the merits of each of the different designs have not been studied experimentally. This paper discusses results of an investigation in which transistors having an interdigitated emitter structure are compared directly with transistors utilizing the matrix emitter structure.I n order to minimize the variations introduced in the device processing the matrix transistor and the interdigitated transistor were designed on the same 20 X 30 mils2 bar. Both devices have the same base area of 3 X 8 mils2 and the same emitter size of 1.25 microns, which is approaching the limit of the present contact photolithography technology. The above design parameters result in a packing density (defined as the ratio of emitter periphery to base area) of 5.0 for the interdigitated geometry and 6.5 for the matrix geometry.Two types of diffusion processes were employed to fabricate the transistors. Optimum transistor performance in the S-band was achieved with f T between 2.5 and 3.0 GHz when the emitters were phosphorus diffused. For the arsenic-diffused emitters, f T can be increased to 4 GHz without increasing the base resistance. However, the higher series resistance associated with the arsenic diffused emitter begins to limit the performance of the matrix structure at higher frequencies.As mentioned above, the unique wafer design allows a direct "sideby-side" comparison of the interdigitated and matrix structures in the absence of process variations. The comparison to be detailed in the paper includes measurements of fT, r'b,, and f,,, over a wide range of bias conditions. Large Eignal measurements in which the power output, power gain, and c...
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