In this paper we present an architectural synthesis system. The system is able to generate multiprocessor architectures from behavioural descriptions. It combines the flexibility of so called high level synthesis systems with the higher throughput rates of DSP synthesis systems. After a short introduction into the CADDY system the impacts of mutual exclusion are briefly discussed. Then a new scheduling algorithm based on delay prediction and a new allocation algorithm based on a graph colouring approach are presented, that take data dependencies in the register assignment into account.
o d u wThe recent improvements in the IC fabrication technology gives the possibility to implement whole systems as one integrated circuit. One major task in the design of a complete system is the selection of a suitable architecture for a given algorithm. To support the designer in exploring the design space, synthesis systems should be able to generate different architectures. Finally the designer can choose the most cost effective solution for his specific problem. This paper presents a synthesis system, which is able to generate an RT-structure from an algorithmic specification. The RT-structure may consist of a various number of processors. The system is integrated into an already existing synthesis framework.
Previous W w kToday two different approaches in high level synthesis can be distinguished. The first are systems like the CATHEDRAL systems [MaRS87],[Cla88] or the PARSIVAL system [HaCo88] that are specially designed to meet the demands in DSP. These systems are able to generate solutions with multiple processors. Also pipelining is widely used to increase the throughput rate necessary for real time DSP applications. But due to the low flexibility in the generated architecture, these systems are more or less restricted to .the implementation of DSP algorithms, such as filters.The other type of systems generates a single microprocessor-like solution from any kind of algorithms. These systems are often referred as high level synthesis systems. As stated in [McPC88] this task can be divided into two major steps the scheduling problem and allocation problem. An overview on currently used scheduling and allocation techniques can be found in [Pau189].
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2024~0/0000/0277$01.0001990 IEEEThe system presented here tries to combine the two approaches and generates multiprocessor solutions but with a more flexible architecture of the generated data path.
Overview of the CADDY Sv-In this paper we want to describe the new parts of the complete system for scheduling and allocation inside the CADDY system [CKR84],[RoCa85],[CaRo89] which is currently being integrated into an industrial environment [DKNP89]. The complete system is shown in figure 1. Overview of the complete Synthesis System c hz] CADDY b m e a r t 8 CW-IOY EWM syntbnl. 0 1mlrml.l dum s l i~~t u r i S u b q s h for rludulhi . d .Ika&. /?g Figure I : Overview on the synthesis steps The first step is compilation of the input specification into the intermediate format. This...
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