Analysis of multi-process VHDL specifications with a Petri net model

Müller, Jörg R.; Kramer, H.

doi:10.1109/eurdac.1993.410679

Cited by 9 publications

(6 citation statements)

References 11 publications

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“…Some worst-case performance analysis techniques for concurrent communicating processes have been proposed before [17,18]. In this study, we use a synchronization driven analysis method.…”

Section: Performance Evaluatormentioning

confidence: 99%

Using GALS architecture to reduce the impact of long wire delay on FPGA performance

Jia

Vemuri

2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

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Interconnect delay is becoming a major roadblock to FPGA performance with technology scaling and growing chip sizes. Globally Asynchronous Locally Synchronous (GALS) design is considered a potential solution to this issue. An important design decision in building a GALS FPGA architecture is to determine the appropriate GALS island size. A large GALS island will reduce the asynchronous communication overhead but the interconnect delay inside an island is increased. On the other hand, asynchronous communication overhead could be a major concern for a small GALS island size. In this paper, we propose a design flow to investigate this tradeoff. The input circuit is first divided into partitions according to the specified GALS island size and each partition is then implemented with commercially available CAD tools. The overall system performance is estimated by a performance evaluator. Experimental results validate our design flow and show a performance improvement of around 20% by adopting a GALS architecture.

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“…Some worst-case performance analysis techniques for concurrent communicating processes have been proposed before [17,18]. In this study, we use a synchronization driven analysis method.…”

Section: Performance Evaluatormentioning

confidence: 99%

Using GALS architecture to reduce the impact of long wire delay on FPGA performance

Jia

Vemuri

2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

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“…A certain number of reduction techniques [6,4,5] allow to obtain a smaller Petri Net, which preserves the underlying VHDL semantic and make the net easier to manage. We can apply two techniques of reduction.…”

Section: Principle Of the Petri Nets Constructionmentioning

confidence: 99%

“…Let Sens the set of all signals s i that appear in the sensitivity list of the process, we note s + f i = + f i Sens and we note s + f i = + f i , s + f i . An analysis is performed for all useful couples d i ; f i 2 Trf t asg with d i 6 if s + f i = ? then if d i 2 + f i it is a cyclic function and otherwise it is a simple combinatorial function.…”

Section: Sensitivity List Analysismentioning

confidence: 99%

Formal analysis of single WAIT VHDL processes for semantic based synthesis

Jacomme

Pétrot

Bawa

1999

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)

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This paper deals with the formal identification of flipflops and latches within VHDL descriptions of hardware systems. Due to the simulation based semantics of VHDL, the existing synthesis tools rely on explicit templates to guarantee memorizing element inference. The approach proposed here is based on a formal representation of VHDL in terms of Interpreted Petri Nets. A Petri Net preserving the simulation semantic is build as a result of VHDL compilation and then reduced to a unique minimal form. A set of equations is extracted and a formal analysis is performed on all cyclic symbol assignments. The result is a RTL VHDL description, synthesizable by any existing synthesis tools. This methodology has been implemented and is illustrated on a set of simple and representative descriptions.

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“…It models all aspects of closed VHDL designs as described in the standard [25] and allows the automatic verification of data-independent properties such as deadlock freedom using Petri net analysis techniques on the "decoloured" net [30]. The Petri net model described in [29] is used to determine access conflicts on global signals but does not model data aspects of VHDL.…”

Section: D(~hmen Herrmann and Pargmannmentioning

confidence: 99%

Translating VHDL into functional symbolic finite-state models

Döhmen

Herrmann

Pargmann

1995

Form Method Syst Des

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Abstract. In this paper we present a method to translate VHDL into symbolic finite-state models. Our method can handle those aspects of VHDL which have a finite representation obtaining the semantics defined in the IEEE statndard. We describe an intermediate representation based on finite automata and its translation into a BDD-based reperesentation. Our model interfaces VHDL with a BDD-based functional symbolic model checker.

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Analysis of multi-process VHDL specifications with a Petri net model

Cited by 9 publications

References 11 publications

Using GALS architecture to reduce the impact of long wire delay on FPGA performance

Using GALS architecture to reduce the impact of long wire delay on FPGA performance

Formal analysis of single WAIT VHDL processes for semantic based synthesis

Translating VHDL into functional symbolic finite-state models

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