Currently, rapid prototyping (RP) products are manufactured by layer-based process; this result may cause RP products to break easily along layers when a bending moment is applied. To prevent RP transtibial sockets from breaking, wrapping a layer of unsaturated polyester resin (UPR) around transtibial sockets to reinforce its flexural strength is proposed. To verify the applicability of resin-reinforced RP socket fabrication, two experimental systems, including a socket sensor measurement and gait analysis system, are used to obtain interface pressures between stump, socket and gait characteristics during stance phase while such type of prosthetic socket is used. A male volunteer with a left below-knee amputation, a twenty-year transtibial socket user, was selected for this study. In the experiments, sensors were pasted on the stump and measurement data was collected at different walking speeds. The results of these experiments showed that the interface pressures were concentrated on pressure-tolerant areas, and the swing phase and stride length of stump increased while the volunteer was walking at a fast speed. The resin-reinforced rapid prototyping sockets have better comfortable quality of fitting because the interface pressures are more concentrated on pressure-tolerant areas including the patella tendon and medial tibia flare while wearing the new type of sockets.
A tri-layer bus system-on-chip (SoC) and a butterfly-path accelerator are used to enhance system-level performance in a sequential minimal optimisation learning core. The tri-layer bus architecture is used to obtain an adequate transfer rate. The butterfly-path accelerator also uses symmetrical access to resolve bottlenecks during linear prediction cepstral coefficients extraction. This novel design increases speed and flexibility without substantially increasing area. For implementation in chip manufacturing, the SoC is synthesised, placed and routed using the TSMC 90 nm technology library. The die size is 2.09 mm × 2.09 mm, and the power consumption is 8.9 mW. Compared with the non-butterfly-path design, the simulation results show that the proposed architecture provides a 2.4-fold speed increase. In addition, clock down-sampling and voltage scaling reduce the power consumed by the proposed chip by a factor of 8.5. The experimental results confirm the improved speed and power that are provided by the proposed architecture and methods.
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