Abstract-Ultra-low-voltage (ULV) floating-gate differential amplifiers are presented. In this paper, we present several different approaches to CMOS ULV amplifier design. Sinh-shaped and tanh-shaped transconductance amplifiers are described. Measured results are provided.
Abstract-This paper presents a novel voltage mode Balanced Ternary Adder (BTA), implemented with Recharged SemiFloating Gate Devices. By using balanced ternary notation, it possible to take advantage of carry free addition, which is exploited in designing a fast adder cell. The circuit operates at 1 GHz clock frequency. The supply voltage is only 1.0 Volt. The circuit is simulated by using Cadence R Analog Design Environment, with CMOS090 process parameters, a 90nm General Purpose Bulk CMOS Process from STMicroelectronics with 7 metal layers. All the capacitors are metal plate capacitors, based on vertical coupling capacitance between stacked metal plates.
This paper presents a multiplier circuit using Balanced Ternary (BT) Notation. The multiplier can multiply both negative and positive numbers, which is one of the advantage able properties of the balanced ternary numbering systems. By using balanced ternary notation, it is possible to take advantage of carry free multiplication, which is exploited in designing a fast multiplier circuit. The circuit is implemented with Recharged Semi-Floating Gate (RSFG) devices. The circuit operates at 1 GHz clock frequency at a supply voltage of only 1.0 Volt. The circuit is simulated by using CadenceRAnalog Design Environment, with CMOS090 process parameters, a 90nm General Purpose Bulk CMOS Process from STMicroelectronics with 7 metal layers.
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