A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices

Abstract

Abstract-This paper presents a novel voltage mode Balanced Ternary Adder (BTA), implemented with Recharged SemiFloating Gate Devices. By using balanced ternary notation, it possible to take advantage of carry free addition, which is exploited in designing a fast adder cell. The circuit operates at 1 GHz clock frequency. The supply voltage is only 1.0 Volt. The circuit is simulated by using Cadence R Analog Design Environment, with CMOS090 process parameters, a 90nm General Purpose Bulk CMOS Process from STMicroelectronics with 7 metal layers. All the capacitors are metal plate capacitors, based on vertical coupling capacitance between stacked metal plates.

Can Ternary Computing Improve Information Assurance?

“…Ternary logic can be made compatible with binary logic by mapping the "−" to a binary "0" and mapping the "+" to a binary "1" [25,26]. Several additional logical operations can be defined to utilize the ternary "0".…”

Arithmetic with binary-encoded balanced ternary numbers

“…Finally, work on ternary number representation and arithmetic has not been limited to the Setun and TERNAC experiments [Halp68], [Eich86], [Gund06], [Gund06a], [Tern13]. Most proposals for ternary arithmetic envisage multivalued signals to encode the three digit values in balanced or standard ternary.…”

Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices

“…Earlier work on this problem was a balanced ternary adder which were presented in Singapore at the ISMVL conference in 2006 [6]. This was a balanced (2,2) ternary adder, it had two balanced ternary inputs (X and Y) and two balanced ternary outputs (S 0 , S 1 ).…”