Power and bandwidth requirements have become more stringent for DRAMs in recent years. This is largely because mobile devices (such as smart phones) are more intensively relying on the use of graphics. Current DDR memory I/Os operate at 5Gb/s with a power efficiency of 17.4mW/Gb/s (i.e., 17.4pJ/b) [1], and graphic DRAM I/Os operate at 7Gb/s/pin [3] with a power efficiency worse than that of DDR. High-speed serial links [5], with a better power efficiency of 1mW/Gb/s, would be favored for mobile memory I/O interface. However, serial links typically require long initialization time (~1000 clock cycles), and do not meet mobile DRAM I/O requirements for fast switching between active, standby, self-refresh and power-down operation modes [4]. Also, traditional baseband-only (or BB-only) signaling tends to consume power super-linearly [4] for extended bandwidth due to the need of power hungry pre-emphasis, and equalization circuits.To overcome aforementioned technical limitations, we propose to implement a Dual (Base+RF) Band Interconnect (DBI) to enable high throughput data rate and low power operation in a mobile DRAM I/O interface. Unlike the conventional BBonly signaling, the proposed DBI signaling, as shown in Fig. 28.1.1, uses both BB and RF bands for simultaneous dual data stream communications, but shares the common transmission line (T-Line). Instead of limiting the baseband operation within its linear-power-consumption region versus the bandwidth, we can now double the interface bandwidth by using DBI and still maintain the linearpower-consumption versus the bandwidth in each of the dual bands. Additionally with forwarded clocking that adds a small overhead to DRAM I/O ( Fig. 28.1.1), the DBI enables simultaneous bidirectional data links [6] as well. By applying such links to DRAM I/O data (DQ) and command/address (C/A), we can greatly reduce the DRAM access time by requesting DRAM read/write-operations simultaneously. Consequently, we can implement bidirectional DRAM I/Os with a much higher aggregate data rate (up to 10Gb/s) and lower power operation (2.5mW/Gb/s).Figure 28.1.2 shows the DBI transceiver schematic of the memory controller side with an RF-band transmitter (RFTX) and a baseband receiver (BBRX). The RFTX contains an LC tank VCO, an amplitude-shift keying (ASK) modulator and a frequency-selective transformer. In RFTX, the VCO first generates RF carrier at 23GHz and continuously modulates M1 and M2 for ASK communication. The data stream D 1(RF) modulates the 23GHz carrier by switching on/off the current flow through M3 and M4 to complete the ASK modulation. The modulated output is then inductively coupled into an off-chip T-Line by way of an on-chip differential transformer. The BBRX amplifies the incoming data stream D 2(BB) using buffers with On-Die Termination (ODT) to set the common mode voltage at the transformer center tap and remove the impedance mismatch. As a result, we transmit and receive D 1(RF) and D 2(BB) data streams concurrently under both differential (RF-band) and common (BB) modes...

No abstract

No abstract

No abstract

No abstract

Summary In this paper, an efficient and highly accurate algorithm for yield‐aware design of pipeline analog to digital converters (ADCs) based on a four‐step approach is presented. First, a general netlist is generated for the data converter building blocks. Then, using an evolutionary method, its best performance sizing is estimated. Finally, the yield gets enhanced to reach a desired value. With the same accuracy, the presented algorithm can achieve yield optimization by approximately five times less computational cost compared with a state‐of‐the‐art MC‐based method. The framework is applied to demonstrate a reliable converter with optimum performance, power consumption, speed and area overhead during a single running process. A prototype 10‐bit resolution, 10‐MS/s pipeline analog to digital converter has been simulated in a 0.18‐µm 1.8‐V CMOS process. Presented results, applying the proposed method, show important advantages in terms of accuracy and efficiency. Copyright © 2016 John Wiley & Sons, Ltd.

No abstract

Abstract-The demand for capacity and off-chip bandwidth to dynamic random-access memory (DRAM) will continue to grow as we integrate more cores onto a die. However, as the data rate of DRAM has increased, the number of dual in-line memory modules (DIMMs) supported on a multi-drop bus has decreased. Therefore, traditional memory systems are not sufficient to meet both these demands. We propose the DIMM tree architecture for better scalability by connecting the DIMMs as a tree. The DIMM tree architecture is able to grow the number of DIMMs exponentially with each level of latency in the tree. We also propose application of multiband radio-frequency interconnect (MRF-I) to the DIMM tree architecture for even greater scalability and higher throughput. The DIMM tree architecture without MRF-I was able to scale up to 64 DIMMs with only an 8% degradation in throughput over an ideal system. The DIMM tree architecture with MRF-I was able to increase throughput by 68% (up to 200%) on a 64-DIMM system over a 4-DIMM system. Finally, we propose the partitioned DIMM tree, which allows the scaling of a main memory system to a many-DIMM memory system while still maintaining high throughput. The partitioned DIMM tree is able to improve throughput by an average of 19% up to 35% over the DIMM tree with 256 DIMMs on a single channel.Index Terms-Integrated circuit interconnections, memory architecture, radio-frequency integrated circuits, random access memory.