Although conventional global navigation satellite systems (GNSS) receivers were originally designed for single signals, studies on multi-signal receiver design have recently been actively conducted to achieve high accuracy, precision, and reliability. However, in order for a multi-signal receiver to support various codes, the receiver should support the generation of individual codes. Therefore, the resulting problem of increased complexity must be solved. This paper proposes a hardware structure for an area-efficient linear feedback shift register (LFSR)-based multi-frequency universal code generator. Whereas the existing universal code generators were configured so that feedback polynomials, output registers, and initial values can be selected by placing read-only memories (ROMs), multiplexers (MUXs), and exclusive ORs (XORs) by register bit, in the case of the proposed universal code generator; the circuit was implemented by applying the hardwiring technique to those register bits that have fixed values. According to the results of field programmable gate array (FPGA) implementation, the proposed LFSR-based universal code generator can improve look up table (LUT) by up to 37% and register by up to 78% when compared to conventional code generators, and LUT by up to 36% when compared to the previous universal code generator. Therefore, the proposed universal code generator is a good candidate for implementing multi-frequency receivers to achieve high precision and high reliability.
In this paper, we analyze the acquisition and tracking performance of signal using a tiered differential polyphase code as the secondary code. The Zadoff-Chu sequence is known to have a CAZAC (Constant Amplitude Zero Auto-Correlation) characteristics. The secondary code generated by differential encoding of the Zadoff-Chu sequence also has the same characteristics as the Zadoff-Chu sequence. Therefore, long integration will give better correlation results. We compare signal acquisition and tracking performance when using the NH sequence and Zadoff-Chu sequence as the secondary code. Monte-carlo simulation is performed using MATLAB. We use the probability of detection and the mean acquisition time for signal acquisition performance and tracking jitter for signal tracking performance.
Recently, multi-frequency multi-constellation receivers have been actively studied, which are single receivers that process multiple global navigation satellite system (GNSS) signals for high accuracy and reliability. However, in order for a single receiver to process multiple GNSS signals, it requires as many code generators as the number of supported GNSS signals, and this is one of the problems that must be solved in implementing an efficient multi-frequency multi-constellation receiver. This paper proposes an area-efficient universal code generator that can support both GPS L1C signals and BDS B1C signals. The proposed architecture alleviates the area problem by sharing common hardware in a time-multiplex mode without degrading the overall system performance. According to the result of the synthesis using the CMOS 65 nm process, the proposed universal code generator has an area reduced by 98%, 93%, and 60% compared to the previous memory-based universal code generator (MB UCG), the Legendre-generation universal code generator (LG UCG), and the Weil-generation universal code generator (WG UCG), respectively. Furthermore, the proposed generator is applicable to all Legendre sequence-based codes.
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