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High-voltage direct current transmission systems are expected to allow the transmission of huge volumes of electricity over long distances. The use of superconducting fault current limiters (SFCLs) based on second-generation (2G) high-temperature superconductor (HTS) coated conductors (CCs) is a promising solution to mitigate fault currents in DC transmission systems. To fabricate a SFCL whose size remains acceptable, which means minimizing the length of the HTS tape used, the tape must sustain a high electric field during the whole fault duration. In this paper, high performance commercial 2G HTS CCs from THEVA (more than 750 A/cm-width at 77 K in self-field), on which a 500 µm thick Hastelloy shunt was soldered, were tested by submitting them to faults of different amplitudes and durations. Measurements revealed that these HTS tapes could sustain any type of fault up to 100 V m−1, lasting up to 50 ms. Three-dimensions finite element simulations were able to reproduce accurately the experiments by using the appropriate temperature dependence of the critical current density and power law index, and by accounting for the variations in the local critical current along the length of the HTS tapes.

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REBCO Coated Conductors with very good characteristics are now easily available in hundreds of meter lengths. Their use for resistive fault current limiter applications is constrained by the variations of the critical current density along the length, which may lead to the appearance of destructive hotspot under ohmic fault conditions. In this paper, we present a light 1D model of Coated Conductor FCL that take into account the critical current density variations along the length, assuming a homogenous temperature in the tape cross section. This assumption is discussed by comparing simulation results for a case of quench propagation under constant current with those obtained with a more refined 2D model. The new 1D model is then compared to small scale experiments of DC FCL with very short transient. Finally it is used to study the influence of tape architecture on the behavior of a MW-class DC Fault Current Limiter with critical current non-uniformities and select a suitable candidate architecture for the realization of such device.

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