In this paper we report on mass metrology used for the characterization of different process steps (etch, clean, cavity etch, HARP deposition and CMP) of shallow trench isolation (STI) module in conventional CMOS technology. We also report on mass metrology for the characterization of plasma doping and on HfO2 high k gate dielectric deposition process. The performance of the mass balance metrology is benchmarked against state of the art metrology, including ellipsometery and Rutherford Backscattering (RBS).
A dry-wet patterning process for La 2 O 3 /HfO 2 -containing high-κ/ metal gate stacks was successfully developed. The process meets the stringent requirements of complete removal of the high-κ layers and metal-containing sidewall residues without inducing silicon recess or undercut. The interaction between the dry etch and wet clean steps was studied. Use of a BCl 3 -based plasma process facilitated the cleaning process as it damages and modifies the high-κ layers in the active area. When the dry etch process ends with a BCl 3 step, La-containing residues were formed inhomogeneously over the wafer within the time scale of hours. These residues could no longer be removed with a wet clean, but were not observed when the dry etch and wet clean processes were integrated. This demonstrates that an integrated etch-clean process enlarges the process window.
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