This paper demonstrates how sodium enhanced oxidation of Si face 4H-SiC results in removal of near-interface traps at the SiO2∕4H-SiC interface. These detrimental traps have energy levels close to the SiC conduction band edge and are responsible for low electron inversion channel mobilities (1–10cm2∕Vs) in Si face 4H-SiC metal-oxide-semiconductor field effect transistors. The presence of sodium during oxidation increases the oxidation rate and suppresses formation of these near-interface traps resulting in high inversion channel mobility of 150cm2∕Vs in such transistors. Sodium is incorporated by using carrier boats made of sintered alumina during oxidation or by deliberate sodium contamination of the oxide during the formation of the SiC∕SiO2 interface.

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We introduce a new experimental setup with a biasing circuit and computer control for electrical power regulation under reversing polarity in Pt microwires with dimensions of 1×10 μm(2). The circuit is computer controlled via a data acquisition board. It amplifies a control signal from the computer and drives current of alternating polarity through the sample in question. Time-to-failure investigations under DC and AC current stress are performed. We confirm that AC current stress can improve the life time of microwires at least by a factor of 10(3) compared to the corresponding time-to-failure under DC current stress.

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We report investigations of MOS and MOSFET devices using a gate oxide grown in the presence of sintered alumina. In contrast to conventionally grown dry or wet oxides these oxides contain orders of magnitude lower density of near-interface traps at the SiO2/SiC interface. The reduction of interface traps is correlated with enhanced oxidation rate. The absence of near-interface traps makes possible fabrication of Si face 4H-SiC MOSFETs with peak field effect mobility of about 150 cm2/Vs. A clear correlation is observed between the field effect mobility in n-channel MOSFETs and the density of interface states near the SiC conduction band edge in n-type MOS capacitors. Stable operation of such normally-off 4H-SiC MOSFET transistors is observed from room temperature up to 150°C with positive threshold voltage shift less than 1 V. A small decrease in current with temperature up to 150°C is related to a decrease in the field effect mobility due to phonon scattering. However, the gate oxides contain sodium, which originates from the sintered alumina, resulting in severe device instabilities during negative gate bias stressing.

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In this work two oxidation methods aimed at improving the silicon face 4H-SiC/SiO 2 interface are compared. One is an oxidation in N 2 O performed in a quartz tube using quartz sample holders and the other is a dry oxidation performed in an alumina tube using alumina sample holders. In n-type metal oxide semiconductor (MOS) capacitors the interface state density near the SiC conduction band edge is estimated using capacitance-voltage (C-V) and thermal dielectric relaxation current (TDRC) measurements. N-channel metal oxide semiconductor field effect transistors (MOSFETs) are characterized by current-voltage (I-V) techniques and the inversion channel mobility is extracted. It is shown that the high inversion channel mobility (154 cm 2 V −1 s −1 ) seen in samples oxidized using alumina correlates with a low interface trap density (3.6 × 10 11 cm −2 ). In the case of N 2 O oxidation the mobility is lower (24 cm 2 V −1 s −1 ) and the interface trap density is higher (1.6 × 10 12 cm −2 ). Room temperature C-V measurements are of limited use when studying traps near the conduction band edge in MOS structures while the TDRC measurement technique gives a better estimate of their density.