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This paper proposes a Petri-net-based specification of cyber-physical systems dedicated to the control of a direct matrix converter with space vector modulation (SVM) and transistor commutation. The technique employed is further applied for hardware implementation in a programmable logic device [namely, field-programmable gate array (FPGA)]. Contrary to the traditional SVM computation methods, concurrency aspects of the digital devices are highly utilized in the presented solution. Therefore, the hardware system is specified by a live and safe Petri net, which is based on the parallelism. Moreover, such a specification can be easily analyzed and verified against the structural properties in order to avoid formal errors and prototyping mistakes (such as deadlocks or non-reachable states). The proposed idea is illustrated by a case-study example of the real prototype of the SVM algorithm. The system has been specified by a live and safe Petri net, analyzed, verified, and finally implemented in the FPGA device. The obtained results of the physical implementation are presented and discussed.

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The paper proposes a novel design technique of cyber-physical systems (CPSs). The system is specified by a Petri net, and further modelled in a hardware description language (HDL) towards final implementation in a programmable device. Contrary to the traditional design methods, the proposed solution is highly focused on the verification aspects. The system is checked three times before the final implementation in hardware. Initially, the Petri-net based specification is formally verified by the application of the model-checking technique. Secondly, software verification of the modelled system is performed. Finally, the hardware verification of the already implemented system is executed. The proposed method is explained by an example of a direct matrix converter (MC) with transistor commutation and space vector modulation (SVM). The main benefits, as well as the limitations, of the proposed solution are discussed and analysed.

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