This paper presents a BJT-based smart CMOS temperature sensor. The analog front-end circuit contains a bias circuit and a bipolar core; the data conversion interface features an incremental delta-sigma analog-to-digital converter. The circuit utilizes the chopping, correlated double sampling, and dynamic element matching techniques to mitigate the effects of process bias and nonideal device characteristics on measurement accuracy. Furthermore, based on the principle of charge conservation, the dynamic range utilization of the ADC increases. We propose a neural network that uses a multilayer convolutional perceptron to calibrate the sensor output results. Using the algorithm, the sensor achieves an inaccuracy of ±0.11 °C (3σ), exceeding the accuracy of ±0.23 °C (3σ) achieved without calibration. We implement the sensor in a 0.18 µm CMOS process, occupying an area of 0.42 mm2. It achieves a resolution of 0.01 °C and has a conversion time of 24 ms.
This paper proposes a low power read-out integrated circuit (ROIC) for multiple sensors having a DC output signal. It comprises a chopper-stabilized instrumentation amplifier (CSIA) followed by a second-order incremental analog-to-digital converter (IADC). The CSIA has a dual-frequency path to effectively eliminate any 1/f noise and offset. A variable gain module (VGM) is also connected to the CSIA to improve its range of potential applications. A CMOS buffer amplifier followed by the CSIA is used to achieve the ROIC's linearity and drive capability. The back-end of the ROIC has a switchedcapacitor IADC to provide a digital output. The correlated double sampling (CDS) technique was used in the IADC's first integrator to reduce the offset and noise. The combination of these techniques enables the ROIC to achieve an input referred offset of 5 μV and a best error voltage of ±0.01 mV. The ROIC was implemented in 0.18 μm CMOS technology. It occupies an area of approximately 2.56 mm2 and consumes 835 μA of current from a 1.6 V of supply voltage.
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