The SoC (System on Chip) design demands for novel architectural and circuital solutions to cope with the global wires issue, pushing the on-chip communication as a crucial and precious resource. In the context of the communication centric paradigm and according to a layered based design, it is foreseen that current on-chip shared bus will be, at least partially, replaced by a micronetwork interconnection implementing a flexible packetbased communication [l]. We state that the availability of an efficient on-chip communication platform is one of the most important enabling factors for the development of efficient and cost effective multi processor SoC in the near and long-term future. This summarypresmts the low cost, high performance on-chip communication network, called Spidergon, developed by the AST fidvanced System Technology) of STMicroelectronics as the possible evolution of STBus technology.The main driving factor of the Spidergon research activity is to explore the complex design space to match a low cost hardware implementation. On that respect we performed the strategic choice of adopting a particular and fixed topology, to exploit the relevant properties for proposing an optimized NoC (Network on Chip) solution. Spidergon NoC is based on a novel scalable, regular, point-to-point topology. The Spidergon network connects a generic even number of nodes N=2n (n=2,3 ... ) as a hidirectional ring in both clockwise, and antklockwise directions uith in addition a cross connection for each couple of nodes. By a formal definition, each node i, with 05 i
Reconfigurable architectures and NoC (Network-onChip) have introduced new research directions for technology and flexibility issues, which have been largely investigated in the last decades. Exploiting run-time adaptivity opens a new area of research by considering dynamic reconfiguration. In this paper, we present the architecture and associated development tools of an heterogeneous reconfigurable SoC focusing on the chosen communication infrastructure. The SOC integrates units of various sizes of reconfiguration granularity. The included NoC approach demonstrates the mentioned benefits and scalability for actual and future SoC design.On a reference CMOS090 implementation the described interconnect system works at the system reference frequency of 200 MHZ sustaining the required run-time bandwidth on a set of reference applications, at a price 10% in area in power consumption with respect to the overall system.
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