Design of a HW/SW communication infrastructure for a heterogeneous reconfigurable processor

Abstract

Reconfigurable architectures and NoC (Network-onChip) have introduced new research directions for technology and flexibility issues, which have been largely investigated in the last decades. Exploiting run-time adaptivity opens a new area of research by considering dynamic reconfiguration. In this paper, we present the architecture and associated development tools of an heterogeneous reconfigurable SoC focusing on the chosen communication infrastructure. The SOC integrates units of various sizes of reconfiguration granularity. The included NoC approach demonstrates the mentioned benefits and scalability for actual and future SoC design.On a reference CMOS090 implementation the described interconnect system works at the system reference frequency of 200 MHZ sustaining the required run-time bandwidth on a set of reference applications, at a price 10% in area in power consumption with respect to the overall system.

Reconfigurable Multi-Array Architecture for Low-Power and High-Speed Embedded Systems

“…It shows good performance for regular code segments in computation intensive domains but requires large amount of area and power consumption. XPP configurable system-on-chip architecture [3] is another example. XPP has 4 × 4 or 8 × 8 reconfigurable array and LEON processor with AMBA bus architecture.…”

“…The nano processors do not also include heavy resources like XPP but it also restricts the range of applicable domains. However, the communication with main processor is faster than [2] or [3] because the processor can access the register-set by coprocessor data transfer instructions. However, limited size of the register-set causes heavy registers-array traffic restricting performance enhancement.…”

“…4 improves the performance by three cycles compared to the SIMD, but for loops with more frequent memory operations, it will have higher performance improvement. [2]; t3 = t3*c [3]; t4 = t4*c [4]; tmp1 = t1+ t2 ; tmp2 = t3+ t4 ; When mapping kernels onto the reconfigurable architecture with loop pipelining, we can consider two mapping techniques: spatial mapping and temporal mapping. Fig.…”

“…I can consider three types of organizations in connecting RAA to the processor. First, the array can be connected to the processor through a system bus as an 'Attached IP' [2,3,8] shown in Fig. 6(a).…”

Dynamic Reconfigurable Networks in NoC for I/O Supported Parallel Applications

“…In spite of above advantages, NoC yet has the flaw that the communication infrastructures cost too much areas and power consumptions compared with the other components like process elements (PE) [17] [18]. The issue becomes more prominent in manycore approach.…”