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Aquesta és una còpia de la versió draft d'un article publicat a IEEE transactions on nanotechnologyhttp://hdl.handle.net/2117/104473 Papandroulikadis, G., Vourkas, I., Abustelema, A., Sirakoulis, G., Rubio, A. Crossbar-based memristive logic-in-memory architecture. "IEEE transactions on nanotechnology", 1 Abril 2017, vol. 16, núm. 3, p. 491-501. DOI: 10.1109/TNANO.2017 © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1Abstract-The use of memristors and resistive random access memory (ReRAM) technology to perform logic computations has drawn considerable attention from researchers in recent years. However, the topological aspects of the underlying ReRAM architecture and its organization have received less attention, as the focus has mainly been on device-specific properties for functionally complete logic gates through conditional switching in ReRAM circuits. A careful investigation and optimization of the target geometry is thus highly desirable for the implementation of logic-in-memory architectures. In this paper, we propose a crossbar-based in-memory parallel processing system in which, through the heterogeneity of the resistive cross-point devices, we achieve local information processing in a state-of-the-art ReRAM crossbar architecture with vertical group-accessed transistors as cross-point selector devices. We primarily focus on the array organization, information storage, and processing flow, while proposing a novel geometry for the cross-point selection lines to mitigate current sneak-paths during an arbitrary number of possible parallel logic computations. We present an analysis of circuit resources, integration density, and logic computation parallelism and prove the proper functioning and potential capabilities of the proposed architecture through SPICE-level circuit simulations of half-adder (HA) and sum-of-products logic functions.

Current advances in emerging memory technologies enable novel and unconventional computing architectures for high-performance and low-power electronic systems, capable of carrying out massively parallel operations at the edge. One emerging technology, ReRAM, also known to belong in the family of memristors (memory resistors), is gathering attention due to its attractive features for logic and in-memory computing; benefits which follow from its technological attributes, such as nanoscale dimensions, low power operation and multi-state programming. At the same time, design with CMOS is quickly reaching its physical and functional limitations, and further research towards novel logic families, such as Threshold Logic Gates (TLGs) is scoped. TLGs constitute a logic family known for its high-speed and low power consumption, yet rely on conventional transistor technology. Introducing memristors enables a more affordable reconfiguration capability of TLGs. Through this work, we are introducing a physical implementation of a memristor-based currentmode TLG (MCMTLG) circuit and validate its design and operation through multiple experimental setups. We demonstrate 2-input and 3-input MCMTLG configurations and showcase their reconfiguration capability. This is achieved by varying memristive weights arbitrarily for shaping the classification decision boundary, thus showing promise as an alternative hardware-friendly implementation of Artificial Neural Networks (ANNs). Through the employment of real memristor devices as the equivalent of synaptic weights in TLGs, we are realizing components that can be used towards an in-silico classifier.Today's conventional computing paradigm is based on the MOSFET transistor and CMOS technology; two cornerstones which have underpinned the development of digital electronics over the last 5 decades. Although there is still optimism for future improvement of CMOS, accumulating scientific evidence indicates the need for advances in both new emerging technologies to replace MOSFETs and in new computer circuits and architectures 1,2 . The former addresses the increasing difficulty of pursuing further downscaling (with its associated drop in reliability 2 ) whilst the latter seeks to address the Von Neumann bottleneck, where increasingly big memories and powerful processors struggle to communicate over a limited interlink whose data transfer capacity doesn't scale fast enough 2-4 .On the computation/architecture front, there has been a sustained effort to develop bio-inspired computation concepts, mostly in the guise of artificial neural network-enabled (ANN) systems. Research on artificial neural networks has thus far spanned the entire interval between the first simplified models of all-or-none hardware neurons 5 and the current state-of-the-art GPU-based ANNs 6-8 . However, one often overlooked example of ANN-like computation can be found in the form of its quantized, digital counterpart, the so-called threshold logic (TL). TL is a model for performing a

With the recent advances of the emerging memories technologies, research are able to implement novel circuits, systems and computer architectures towards the design of high-performance and low-power electronic systems able to accelerate and/or optimize the functionality of many computer workflows. One emerging technology, the ReRAM/memristor is gathering attention due to its inherent advantages for logic and memory computing systems. At the same time, CMOS circuit design seems to have reached a limit, where easily optimized circuit solutions cannot be found. Thus, further research towards novel logic gate families, such as Threshold Logic Gates (TLGs), a logic family known for its high-speed and low power consumption, is needed. Although many implementation concepts of TLG circuit are using memristors, few of these implementations are based on physical ReRAM devices. In this work we are proposing a memristor-based threshold logic gate design towards the optimization of computer workflows. The presented results include a physical implementation of the proposed circuits which supports the concept of memory-based reconfigurable computing circuits and systems.

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