Multi-state memristive nanocrossbar for high-radix computer arithmetic systems

Papandroulidakis, Georgios; Vourkas, Ioannis; Sirakoulis, Georgios Ch.; Stavrinides, Stavros G.; Nikolaidis, S.

doi:10.1109/nano.2015.7388682

Cited by 5 publications

(2 citation statements)

References 15 publications

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“…This algorithm, as well as all of its alternatives, quantum computing excluded [5], requires a long computation time when dealing with complex graphs. To overcome this, parallel computing becomes a very good alternative in reducing computing time and further improve efficiency [6][7][8].…”

Section: Introductionmentioning

confidence: 99%

GERARD: GEneral RApid Resolution of Digital Mazes Using a Memristor Emulator

Dopazo¹,

Benito²,

Camps³

et al. 2021

Preprint

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In this paper, a system of searching for optimal paths is developed and concreted on a FPGA. It is based on a memristive emulator, used as a delay element, by configuring the test graph as a memristor network. A parallel algorithm is applied to reduce computing time and increase efficiency. The operation of the algorithm in Matlab is checked beforehand and then exported to two different Intel FPGAs: a DE0-Nano board and an Arria 10 GX 220 FPGA. In both cases reliable results are obtained quickly and conveniently, even for the case of a 300x300 nodes maze.

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Section: Introductionmentioning

confidence: 99%

GERARD: GEneral RApid Resolution of Digital Mazes Using a Memristor Emulator

Dopazo¹,

Benito²,

Camps³

et al. 2021

Preprint

Self Cite

View full text Add to dashboard Cite

show abstract

Section: Introductionmentioning

confidence: 99%

GERARD: GEneral RApid Resolution of Digital Mazes Using a Memristor Emulator

Dopazo

Benito

Camps

et al. 2021

Physics

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Memristive technology is a promising game-changer in computers and electronics. In this paper, a system exploring the optimal paths through a maze, utilizing a memristor-based setup, is developed and concreted on a FPGA (field-programmable gate array) device. As a memristor, a digital emulator has been used. According to the proposed approach, the memristor is used as a delay element, further configuring the test graph as a memristor network. A parallel algorithm is then applied, successfully reducing computing time and increasing the system’s efficiency. The proposed system is simple, easy to scale up and capable of implementing different graph configurations. The operation of the algorithm in the MATLAB (matrix laboratory) programming enviroment is checked beforehand and then exported to two different Intel FPGAs: a DE0-Nano board and an Arria 10 GX 220 FPGA. In both cases, reliable results are obtained quickly and conveniently, even for the case of a 300 × 300 nodes maze.

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Direct state transfer in MLC based memristive ReRAM devices for ternary computing

Fey

Reuben

2020

2020 European Conference on Circuit Theory and Design (ECCTD)

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Multi-state memristive nanocrossbar for high-radix computer arithmetic systems

Cited by 5 publications

References 15 publications

GERARD: GEneral RApid Resolution of Digital Mazes Using a Memristor Emulator

GERARD: GEneral RApid Resolution of Digital Mazes Using a Memristor Emulator

GERARD: GEneral RApid Resolution of Digital Mazes Using a Memristor Emulator

Direct state transfer in MLC based memristive ReRAM devices for ternary computing

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