Arbiters are the most critical element to manage a shared resource. Many arbiters in the literature are asynchronous, in order to improve concurrency and make the performance independent from the working frequency of the requesting clients. However, in asynchronous designs, architectural imbalances or variability can affect impartiality, such as latency equalization and arbitration fairness. Such a problem has largely not been taken into account in previous designs and experimental results. This work aims to perform an accurate rebalancing for N-way arbiters, using a new architecture, based on a tree structure. The proposed architecture drastically mitigates various forms of impartiality, as well as enhances overall robustness. The design is also scalable and highly performance-oriented. A detailed comparison of several post-layout N-way arbiter models is included. Results show significant benefits over most critical design costs. 21st IEEE International Symposium on Asynchronous Circuits and Systems1522-8681/15 $31.00

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MMU-less embedded systems are the state of the art solution for deeply embedded computing environments. Thanks to the rapid evolution of such devices, nowadays applications that run on top of them are evolving from simple control tasks to more complex applications that involve an Operating System (OS). At the same time, cost budget remains unchanged in spite of the growing performance requirements. For this reason, traditional code loading and execution techniques like full code shadowing or execute-in-place may lead to a performance bottleneck. Even demand paging strategies lack consensus due to the customization and the complexity of the software infrastructure dealing with the memory management. The objective of this work is to implement a transparent hardware-based demand paging strategy for code loading and execution, targeting MMU-less embedded systems. This approach consists of making the system interconnect aware of the memory map, without burdening on the legacy OS code, application code and on the compilation framework. This approach materializes lower boot-up latency and shorter application execution time with respect to traditional loading and executing schemes