Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Systems

Bertozzi, Davide; Miorandi, Gabriele; Ghiribaldi, Alberto; Burleson, Wayne; Sadowski, Greg; Bhardwaj, Kshitij; Jiang, Weiwei; Nowick, Steven M.

doi:10.1109/mm.2020.3002790

Cited by 10 publications

(10 citation statements)

References 28 publications

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“…We follow a similar approach as in previous studies [8], [14], [16], measuring the static performance of the message bus and comparing it with existing works. This method provides a better reflection of the message bus's performance at the circuit level, independent of factors such as topology and routing algorithms.…”

Section: A Comparison With State-of-the-artmentioning

confidence: 99%

“…TaBuLA [14] is a two-phase bundled-data router with Mousetrap controller, which is an asynchronous pipeline controller using latch instead of flip-flop. It also has gone through several generations [7].…”

Section: A Comparison With State-of-the-artmentioning

confidence: 99%

“…The aforementioned NoCs typically employ traditional asynchronous communication protocols for data communication, including Bundled Data (BD) and Quasi Delay Insensitive (QDI). Some asynchronous NoCs utilize the BD transmission protocol [5]- [9], [14], where asynchronous pipelines such as Click, Mousetrap, and Latch Controller are used as control paths to generate local clock signals. To ensure functional correctness, additional timing constraints must be met between handshake signals and data.…”

Section: Introductionmentioning

confidence: 99%

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A Lightweight and High-Throughput Asynchronous Message Bus for Communication in Multi-Core Heterogeneous Systems

Zeng,

Wang,

Cong

et al. 2024

IEEE Access

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In multi-core heterogeneous systems, communication on the data bus/NoC (Network-on-Chip) is complex. To ensure low-latency transmission of high-level messages, such as control messages, configuration instructions, and status information, while maintaining the efficiency of data bus/NoC transmission, we propose the concept of a message bus. In this paper, we present a lightweight and high-throughput asynchronous message bus capable of receiving and forwarding messages from different synchronous domains. A Quasi-Synchronous communication mechanism is proposed, where flits from the transmitter can be transmitted at fixed intervals without waiting for the ready signal from the receiver. This resolve the additional latency introduced by asynchronous handshaking, particularly in long-wire transmissions. Instead of flit-level handshaking, we introduce a packet-level flow control mechanism to avoid data overflow. Furthermore, we propose a novel Asynchronous Blocking Retransmission Buffer (ABRB) to address the communication congestion where subsequent packets are blocked by preceding ones. The packets can be sequentially written into the ABRB, enabling partial parallel transmission. For various benchmarks, the proposed asynchronous message bus achieves significant performance and energy consumption improvements compared to the synchronous baseline, at the cost of some additional area overhead and more design effort.

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Section: A Comparison With State-of-the-artmentioning

confidence: 99%

Section: A Comparison With State-of-the-artmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Lightweight and High-Throughput Asynchronous Message Bus for Communication in Multi-Core Heterogeneous Systems

Zeng,

Wang,

Cong

et al. 2024

IEEE Access

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“…Therefore, solutions to avoid the development of a custom tool flow are increasingly being investigated: in [76]- [78], the application of specific constraints to industrial digital CAD tools allows automatically optimizing the timing closure of asynchronous bundled-data circuits. This idea was recently applied in the context of networkon-chips (NoCs), where Bertozzi et al demonstrate significant power-performance-area improvements for asynchronous NoCs compared to synchronous ones, while maintaining an automated flow based on standard CAD tools [79]. Leveraging the efficiency of asynchronous circuits with a standard digital tool flow may soon become a key element to support largescale integration of neuromorphic systems.…”

Section: B Digital Designmentioning

confidence: 99%

Bottom-Up and Top-Down Neural Processing Systems Design: Neuromorphic Intelligence as the Convergence of Natural and Artificial Intelligence

Frenkel¹,

Bol²,

Indiveri³

2021

Preprint

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While Moore's law has driven exponential computing power expectations, its nearing end calls for new avenues for improving the overall system performance. One of these avenues is the exploration of new alternative brain-inspired computing architectures that promise to achieve the flexibility and computational efficiency of biological neural processing systems. Within this context, neuromorphic intelligence represents a paradigm shift in computing based on the implementation of spiking neural network architectures tightly co-locating processing and memory. In this paper, we provide a comprehensive overview of the field, highlighting the different levels of granularity present in existing silicon implementations, comparing approaches that aim at replicating natural intelligence (bottom-up) versus those that aim at solving practical artificial intelligence applications (top-down), and assessing the benefits of the different circuit design styles used to achieve these goals. First, we present the analog, mixed-signal and digital circuit design styles, identifying the boundary between processing and memory through time multiplexing, in-memory computation and novel devices. Next, we highlight the key tradeoffs for each of the bottom-up and top-down approaches, survey their silicon implementations, and carry out detailed comparative analyses to extract design guidelines. Finally, we identify both necessary synergies and missing elements required to achieve a competitive advantage for neuromorphic edge computing over conventional machine-learning accelerators, and outline the key elements for a framework toward neuromorphic intelligence.

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“…The second interesting method is determining the kernel [29][30][31], consisting of determining the dominant states of the sequential system from a subset of all states, and then implementing a separate, smaller element performing operations only for dominant states systems. The third interesting method is the implementation of the system in the Globally Asynchronous Locally Synchronous (GALS) architecture [32][33][34], involving decomposition of a locally synchronous system through which data are exchanged via an asynchronous bus, and the clock frequency of each module is individually adapted to the needs of this module.…”

Section: Introductionmentioning

confidence: 99%

Low Power QC-LDPC Decoder Based on Token Ring Architecture

2020

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The article presents an implementation of a low power Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder in a Field Programmable Gate Array (FPGA) device. The proposed solution is oriented to a reduction in dynamic energy consumption. The key research concepts present an effective technology mapping of a QC-LDPC decoder to an LUT-based FPGA with many limitations. The proposed decoder architecture uses a distributed control system and a Token Ring processing scheme. This idea helps limit the clock skew problem and is oriented to clock gating, a well-established concept for power optimization. Then the clock gating of the decoder building blocks allows for a significant reduction in energy consumption without deterioration in other parameters of the decoder, particularly its error correction performance. We also provide experimental results for decoder implementations with different QC-LDPC codes, indicating important characteristics of the code parity check matrix, for which an energy-saving QC-LDPC decoder with the proposed architecture can be designed. The experiments are based on implementations in the Intel Cyclone V FPGA device. Finally, the presented architecture is compared with the other solutions from the literature.

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Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Systems

Cited by 10 publications

References 28 publications

A Lightweight and High-Throughput Asynchronous Message Bus for Communication in Multi-Core Heterogeneous Systems

A Lightweight and High-Throughput Asynchronous Message Bus for Communication in Multi-Core Heterogeneous Systems

Bottom-Up and Top-Down Neural Processing Systems Design: Neuromorphic Intelligence as the Convergence of Natural and Artificial Intelligence

Low Power QC-LDPC Decoder Based on Token Ring Architecture

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