Abstract-A model based on information theory, which allows yield managers to determine optimal portfolio of yield analysis technologies for both the R&D and volume production environments, is presented. The information extraction per experimentation cycle and information extraction per unit time serve as benchmarking metrics for yield learning. They enable yield managers to make objective comparisons of apparently unrelated technologies. Combinations of four yield analysis tools-electrical testing, automatic defect classification, spatial signature analysis and wafer position analysis-are examined in detail to determine the relative value of ownership of different yield analysis technologies.

Abstract-A model based on information theory, which allows yield managers to determine optimal portfolio of yield analysis technologies for both the R&D and volume production environments, is presented. The information extraction per experimentation cycle and information extraction per unit time serve as benchmarking metrics for yield learning. They enable yield managers to make objective comparisons of apparently unrelated technologies. Combinations of four yield analysis tools-electrical testing, automatic defect classification, spatial signature analysis and wafer position analysis-are examined in detail to determine the relative value of ownership of different yield analysis technologies.

A number of quality control and yield improvement techniques are used in the H P Fort Collins IC wafer fabrication line. Four of these are described, with examples of how each has improved quality and yield. (1) Silicon wafer measurements obtained from the vendor or made at incoming inspection are correlated with device parameters and chip yield.( 2 ) Control charts on the manufacturing line are generated on-line. from monitor wafer data entered by operators, giving immediate feedback. In addition, a daily summary report lists any chart out of control. In certain instances it is necessary to improve the process ca ability of an operation. A feedback technique is u s e f t o do this for operations which have a predictable systematic drift. (3) Individual wafer positions in critical operations are automatically recorded throughout the fabrication line. This greatly facilitates correlation of input to out ut parameters and pinpoints the root cause of levice parameter, or chip yield fluctuations. (4ThC$d correlation of the myriad of data obtained throughout the fabrication and wafer test areas is done with a common data base and tools which transform the raw data into an optimum form for analysis.

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