Multirate signal processing is critical to realizing the digital frequency converter in WLAN technologies. In this paper, we focus on designing and analyzing the different structures of decimators that support WLAN-b applications to reduce the frequency by 12 for an IEEE. The structure modeling of the decimator used Simulink. Implementing a single-stage decimator required a higher-order filter, extra storage space, and a long simulation time. Results showed that the necessary storage elements for 2-stage design are 55% and for 3-stage design is 65% of single stage. For 133 MHz WLAN-b application, a two-stage decimator is proved to be efficient.
The first verified capacity-achieving codes were developed by Arikan called “polar codes.” It has gained significant attention due to their low encoding and decoding process complexity and optimum capacity-achievement process. In the original form of polar codes, the decoder has the inferior performance with finite ‘block-lengths' as compared to the LDPC codes, therefore, the successive cancellation decoder (“SCD”) for the polar codes is a very important element in order to provide a capacity theorem, but it comprises complexity at a larger number of iterations that is not applicable for the point of view of lower latency application. Therefore, in this article we proposed a modified SCD that rearranges the stages but it can cause decoder performance degradation, so we applied a novel design rule of the polar codes in order to match with our MSCD model. In the result analysis section, we show the effectiveness of our proposed model that tends to have higher performance rate as compared to standard SCD.
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