Design of Decimation Filters for Wireless Local Area Network Applications

Abstract

Multirate signal processing is critical to realizing the digital frequency converter in WLAN technologies. In this paper, we focus on designing and analyzing the different structures of decimators that support WLAN-b applications to reduce the frequency by 12 for an IEEE. The structure modeling of the decimator used Simulink. Implementing a single-stage decimator required a higher-order filter, extra storage space, and a long simulation time. Results showed that the necessary storage elements for 2-stage design are 55% and for 3-stage design is 65% of single stage. For 133 MHz WLAN-b application, a two-stage decimator is proved to be efficient.