J.L.Autran 2 andS.Deleonibus 1 1 CEA/LETIMINATEC,17ruedesMartyrs,38054Grenoble,France; 2 L2MP,TechnopôledeChâteau-Gombert,13451Marseille,France Tel:+33438782429,Fax:+33438789456,vincent.barral@cea.fr For the first time, we have extracted the ballisticity rates of strained and unstrained nFully Depleted Silicon On Insulator devices with gate lengths down to 10nm. Thanks to a new fully experimental extraction methodology taking into account multi subbandpopulation,wedemonstratethatstraintakesactivelypartin quasiballisticdraincurrentimprovementthankstoa22%injection velocityenhancement,whichwillbecomethepredominanttransport parameterforthenextgenerationofCMOSdevices.Inaddition,we find that strained channel ballisticity rates are slightly greater than unstrained ones whatever the considered temperature and gate length.Thisrateimprovementcanbecloselyrelatedtothemobility gainforshortchannelarchitectures. Fully Depleted strained Silicon On Insulator transistors (FDsSOI)offeranattractivesolutionforthe32nmtechnologynode and beyond, thanks to excellent electrostatic control and transport properties [1,2]. While the impact of biaxial tensile strain on mobilityhasbeenextensivelystudied,itsinfluenceonquasiballistic MOSFETs needs to be clarified. Indeed, in this regime, the drain currentisgovernedbytheinjectionvelocityinthechannelv inj and thebackscatteringcoefficientr(eq.(1),TableI)[36],whereristhe probability for a carrier to be backscattered to the source after an interaction in the channel (Fig. 1). In this work, we investigate for the first time the influence of strain on backscattering coefficients and carrier injection velocities in ultrashort FDSOI devices with gatelengthsdownto10nm. WehavecharacterizedunstrainedandstrainedFDSOItransistors withgatelengths(L G )downto10nmattemperaturesranging from 50K to 296K. All the transistors have an advanced gate stack composed of 3nm HighK gate dielectric (HfO 2 ) and 10nm TiN + 50nm polysilicon ( Fig. 2), and 10nm channel thickness [7]. Capacitance measurements revealed a 1.7nm Equivalent Oxide Thickness (EOT). The strained devices were fabricated on strained SOI wafers obtained by SmartCut TM process, from biaxial tensily strained(001)Si/relaxedSi 0.8 Ge 0.2 epitaxiallayers.Wemeasuredup to29%improvementofthesaturationcurrenton10nmgatelength FDsSOI devices with respect to the FDSOI and up to 13% for the 30nm strained structure, at an inversion charge density (N INV ) of 7.610 12 cm 2 (Fig.3). As summarized in Table I, we have determined a new fully experimental backscatterin...
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