Will strain be useful for 10nm quasi-ballistic FDSOI devices? An experimental study

Abstract

J.L.Autran 2 andS.Deleonibus 1   1 CEA/LETIMINATEC,17ruedesMartyrs,38054Grenoble,France; 2 L2MP,TechnopôledeChâteau-Gombert,13451Marseille,France Tel:+33438782429,Fax:+33438789456,vincent.barral@cea.fr   For the first time, we have extracted the ballisticity rates of strained and unstrained nFully Depleted Silicon On Insulator devices with gate lengths down to 10nm. Thanks to a new fully experimental extraction methodology taking into account multi subbandpopulation,wedemonstratethatstraintakesactivelypartin quasiballisticdraincurrentimprovementthankstoa22%injection velocityenhancement,whichwillbecomethepredominanttransport parameterforthenextgenerationofCMOSdevices.Inaddition,we find that strained channel ballisticity rates are slightly greater than unstrained ones whatever the considered temperature and gate length.Thisrateimprovementcanbecloselyrelatedtothemobility gainforshortchannelarchitectures.   Fully Depleted strained Silicon On Insulator transistors (FDsSOI)offeranattractivesolutionforthe32nmtechnologynode and beyond, thanks to excellent electrostatic control and transport properties [1,2]. While the impact of biaxial tensile strain on mobilityhasbeenextensivelystudied,itsinfluenceonquasiballistic MOSFETs needs to be clarified. Indeed, in this regime, the drain currentisgovernedbytheinjectionvelocityinthechannelv inj and thebackscatteringcoefficientr(eq.(1),TableI)[36],whereristhe probability for a carrier to be backscattered to the source after an interaction in the channel (Fig. 1). In this work, we investigate for the first time the influence of strain on backscattering coefficients and carrier injection velocities in ultrashort FDSOI devices with gatelengthsdownto10nm.   WehavecharacterizedunstrainedandstrainedFDSOItransistors withgatelengths(L G )downto10nmattemperaturesranging from 50K to 296K. All the transistors have an advanced gate stack composed of 3nm HighK gate dielectric (HfO 2 ) and 10nm TiN + 50nm polysilicon ( Fig. 2), and 10nm channel thickness [7]. Capacitance measurements revealed a 1.7nm Equivalent Oxide Thickness (EOT). The strained devices were fabricated on strained SOI wafers obtained by SmartCut TM  process, from biaxial tensily strained(001)Si/relaxedSi 0.8 Ge 0.2 epitaxiallayers.Wemeasuredup to29%improvementofthesaturationcurrenton10nmgatelength FDsSOI devices with respect to the FDSOI and up to 13% for the 30nm strained structure, at an inversion charge density (N INV ) of 7.610 12 cm 2  (Fig.3).   As summarized in Table I, we have determined a new fully experimental backscatterin...

Ultra-thin films and multigate devices architectures for future CMOS scaling

“…The conservation and enhancement of strain can be observed in very thin layers with small gate lengths. The saturation current can be improved by 40% at the L g =18 nm level by combining strain and ballistic transport [34,35]. I off levels in the pA/µm range have been obtained in these devices with Si thicknesses as low as 2.5 nm [35] (Figures 9 and 10).…”

“…Lg=18 nm FDSOI n channels shown inFigure 9demonstrate a +40% saturation current and a low leakage current for Lg=18 nm because of additive strain and ballistic transport contributions[34,35].…”

“…Lg=18 nm strained FDSOI channel MOS-FETS integration can be controlled at a thickness of 2.5 nm with a HiK/Metal gate stack[34,35].…”

Investigations of the ionizing radiation induced effects in ultra-thin strained-silicon layers on insulator using confocal microscopy measurements

“…In this context, Silicon-On-Insulator (SOI) technology is increasingly used to process high performance and low power circuits. The planar SOI technology is an excellent candidate to reach specifications for future technologies [1] but their performances could be improved with innovative technological options such as: a front gate stack including a high permittivity (high-k) dielectric and a metal gate, or increased carrier mobilities due to mechanical stress induced in the active silicon area [2][3][4][5][6].…”

Gate-all-around technology: Taking advantage of ballistic transport?

“…(4). Theoretical dependence of v sat from[31] and v inj[32] are given. Inset: FDSOI extraction from[32].Fig.…”