A 20-nm physical gate length NMOSFET featuring 1.2 nm gate oxide, shallow implanted source and drain and BF<sub>2</sub> pockets

Deleonibus, S.; Caillat, C.; Guégan, G.; Heitzmann, M.; Nier, M.E.; Tedesco, S.; Dal’zotto, B.; Martín, F.; Mur, P.; Papon, A.M.; Lecarval, G.; Biswas, S.; Souil, D.

doi:10.1109/55.830972

Cited by 35 publications

(10 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Transistors with very short channel lengths, to below 10 nm, have been made and studied (Deleonibus et al 2000, Doris et al 2002, Doyle et al 2002, Bertrand et al 2004. Experimental fabrication methods, not necessarily adaptable to low-cost manufacturing, are needed for the very small dimensions involved.…”

Section: Short Channel Experimentsmentioning

confidence: 99%

Physical limits of silicon transistors and circuits

2005

View full text Add to dashboard Cite

A discussion on transistors and electronic computing including some history introduces semiconductor devices and the motivation for miniaturization of transistors. The changing physics of field-effect transistors and ways to mitigate the deterioration in performance caused by the changes follows. The limits of transistors are tied to the requirements of the chips that carry them and the difficulties of fabricating very small structures. Some concluding remarks about transistors and limits are presented.

show abstract

Section: Short Channel Experimentsmentioning

confidence: 99%

Physical limits of silicon transistors and circuits

2005

View full text Add to dashboard Cite

show abstract

“…However, the impact of Coulomb scattering by dopants on transport is non negligible even in the 5 nm range channel lengths [3,4]. Superhalo doping is efficient to improve SCE and DIBL in 16 nm finished gate length ( Fig.…”

Section: Issues Related To Non Stationary Transportmentioning

confidence: 99%

“…It contributes to the leakage component of power consumption. 1.4 nm thin SiO 2 is usable without affecting devices reliability [3,[7][8][9].…”

Section: Issues Related With Decananometer Gate Length Devicesmentioning

confidence: 99%

Physical and technological limitations of NanoCMOS devices to the end of the roadmap and beyond

Deleonibus

2006

Eur. Phys. J. Appl. Phys.

Self Cite

View full text Add to dashboard Cite

Abstract. Since the end of the last millenium, the microelectronics industry has been facing new issues as far as CMOS devices scaling is concerned. Linear scaling will be possible in the future if new materials are introduced in CMOS device structures or if new device architectures are implemented. Innovations in the electronics history have been possible because of the strong association between devices and materials research. The demand for low voltage, low power and high performance are the great challenges for the engineering of sub 50 nm gate length CMOS devices. Functional CMOS devices in the range of 5 nm channel length have been demonstrated. The alternative architectures allowing to increase devices drivability and reduce power consumption are reviewed. The issues in the field of gate stack, channel, substrate, as well as source and drain engineering are addressed. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. By introducing new materials (Ge, diamond/graphite carbon, HiK, . . . ), Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating also new disruptive devices. For example, the association of C-diamond with HiK, as a combination for new functionalized Buried Insulators, will bring new ways of improving short channel effects and suppress self-heating. Because of the low parasitics required to obtain high performance circuits, alternative devices will hardly compete against logic CMOS. (Fig. 1) has accelerated the scaling of CMOS devices to lower dimensions continuously despite the difficulties that appear in device optimization. PACSHowever, uncertainties about lithography, economics and physical limitations will probably slow down the evolution. For the first time, since the introduction of poly gate in CMOS devices process, showstoppers other than lithography appear to be attracting special attention and could require some breakthrough or evolution if we want to continue scaling at the same rate. Design could also be affected by this evolution.Which are the main showstoppers for CMOS scaling? In this paper, we focus on the possible solutions and guidelines for research in the next years in order to propose solutions to enhance CMOS performance before we need to skip to alternative devices. In other words, how can we offer a second life to CMOS?To that respect, the roadmap distinguishes today three types of products: High Performance (HP) (Fig. 1), Low a e-mail: sdeleonibus@cea.fr Operating Power (LOP) and Low Standby Power (LSTP) devices. In the HP case, a historical fact will happen by the 32 nm node: the contribution of static power dissipation will become higher than the dynamic power contribution to the total power consumption! This main fact could affect the MOSFET saturation current as can be observedArticle published by EDP Sciences and available at

show abstract

“…Hence, estimation of the channel length is a really important and difficult problem. Nevertheless, thanks to both, the extension SIMS profile and the gate length measurement (TEM and MEB observations), the metallurgical channel length can be estimate to roughly 4-5 nm [7] in the case of the 20 nm gate length transistor. For these types of device, channel doping approaches 10 18 at cm −3 , and consequently electron mobility is expected to be of the order of 230 cm 2 (Vs) −1 which yield to scattering lengths of approximately 5.5 nm [8].…”

Section: Simple Approachmentioning

confidence: 99%

“…Junctions are finally activated with a 950 • C/15 s rapid thermal annealing (RTA). Finally, 17 nm S/D extension junction depth resulted from the initially 11 nm deep as implanted profile [7]. A TEM photograph of a 20 nm gate length transistor, obtained using this process flow, is presented in Fig.…”

Section: Introductionmentioning

confidence: 99%

Ultimate sub-25 nm gate length NMOSFETs transport at 293 and 77 K

Bertrand

Deleonibus

Souil

et al. 2000

Superlattices and Microstructures

View full text Add to dashboard Cite

A 20-nm physical gate length NMOSFET featuring 1.2 nm gate oxide, shallow implanted source and drain and BF₂ pockets

Cited by 35 publications

References 6 publications

Physical limits of silicon transistors and circuits

Physical limits of silicon transistors and circuits

Physical and technological limitations of NanoCMOS devices to the end of the roadmap and beyond

Ultimate sub-25 nm gate length NMOSFETs transport at 293 and 77 K

Contact Info

Product

Resources

About

A 20-nm physical gate length NMOSFET featuring 1.2 nm gate oxide, shallow implanted source and drain and BF2 pockets

Cited by 35 publications

References 6 publications

Physical limits of silicon transistors and circuits

Physical limits of silicon transistors and circuits

Physical and technological limitations of NanoCMOS devices to the end of the roadmap and beyond

Ultimate sub-25 nm gate length NMOSFETs transport at 293 and 77 K

Contact Info

Product

Resources

About

A 20-nm physical gate length NMOSFET featuring 1.2 nm gate oxide, shallow implanted source and drain and BF₂ pockets