Symbolic timing verification is a powerfur extension to traditional constraint checking that allows delays and constraints to be expressed as symbolic variables. In this paper, we present an approach to symbolic timing verification using constraint logic programming techniques. The techniques are quire powerful in that they yield not only simple bounds on delays but also relate the delays in linear inequalities so that tradeoffs are apparent. We model circuits as communicating processes and our current implementation can verifr a large class of h d synchronous and asynchronous specifications. The utility of the approach is illustrated with some examples.
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