We developeda new APC technique, available to achieve no pattern-layout-dependence. for reducing lot-tolot post-etch gate-CD variation and tracking them on a target for 40nm gate fabrication. The model equalion, adapted in our APC system, was a linear equation ofgate CD loss as afunction ofS02/02 mixtzrre ratio at a constant over etch time. It had a l0nm afcontrollable range ofgate CD etching loss with the its iso-to-dense difference within i l n m .
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