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An analysis of a ternary single electron tunneling phase logic element is presented. The analysis is based on Monte Carlo simulations and an analytical treatment of a resistively loaded tunneling junction at low temperatures. We show that tristable operation can be obtained over a 19% dc bias operating range by optimizing the pump frequency and amplitude. For large ac frequencies, our optimizations also show that simple linear relationships exist between the optimal parameters (the optimal dc bias and pump amplitude) and frequency. Finally, we show that the ternary phase state of a clocked element can be controlled by an input signal provided that the clock turn-on is not too abrupt. The results should be of use in the design of ternary and other multilevel tunneling phase logic families.

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The introduction of high-speed backplane transceivers inside FPGAs has addressed critical issues such as the ease in scalability of performance, high availability, flexible architectures, the use of standards, and rapid time to market. These have been crucial to address the ever-increasing demand for bandwidth in communication and storage systems [1][2][3], requiring novel techniques in receiver (RX) and clocking circuits. Figure 3.3.1 shows the transceiver architecture with reconfigurable clock generation consisting of two fractional-N LC PLLs per quad and a ring PLL per channel. Since the receiver and the transmitter (TX) require half-rate clock frequencies, the LC PLLs must cover a frequency range of 8 to 16.375GHz for data-rates of 16 to 32.75Gb/s. Lower data-rates are covered by dividing the frequency of the LC PLLs. Each PLL has two LC oscillators to provide a wide tuning range (>45% each) and these two PLLs have an overlap to allow two independent frequencies around 10G standards (covering 9.5 to 13.1GHz). The PLL consists of synchronized CMOS down-counter frequency divider and a programmable sigma-delta (ΣΔ) modulator. The fractional PLL can be configured in either a MASH 1-1 (2 nd order) or MASH 1-1-1 (3 rd order) architecture by programming the (ΣΔ) modulator. The frequency resolution is also programmable from 12 to 24 bits in steps of 4 bits.Each LC PLL is followed by a passive wide-range 2 nd order polyphase filter (PPF) [4] for quadrature generation for high data-rates (>16.375Gb/s). For lower data-rates, a frequency divider divides the LC PLL frequency by two and produces quadrature signals. A multiplexer selects the PPF or the divider output depending on the speed of operation. The PPF circuit uses a two-stage constant-phase topology whose pole locations are chosen to track the frequency range of the preceding PLL. Poles are selected such that over PVT variations magnitude differences are within the tolerable range. A low-distortion linear buffer ensures low harmonic distortion to minimize I/Q error.The differential high-speed I and Q clock signals are routed to the four transceiver channels. A long chain of CML buffers achieve good supply-noise immunity but suffer DC-offset accumulation and I/Q mismatch errors. A capacitive-degenerated CML buffer is inserted in every three buffer stages to attenuate DC gain as shown in Fig. 3.3.1. An additional duty-cycle correction (DCC) and I/Q calibration scheme is implemented in each transceiver channel to ensure good phase-interpolator (PI) linearity, which impacts receiver jitter tolerance margin [5]. Figure 3.3.2 shows the top-level block diagram of the clock DCC and I/Q correction scheme that can be used for both foreground and background calibrations. The duty-cycle distortion (DCD) is corrected for both I and Q phases prior to I/Q correction. The DCC and I/Q correction share the analog front-end with an auto-zeroed pre-amplifier to cancel out the offsets. The DCC correction scheme utilizes capacitor degeneration and 7b current DAC along with digital cali...

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