A Low-Power 0.5–6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs

Savoj, Jafar; Hsieh, Kenny; An, Fu-Tai; Gong, Jian; Im, Jungho; Jiang, Xuewen; Jose, Anup; Kireev, Vassili; Lim, Siok-Wei; Roldan, Arianne; Turker, Didem; Upadhyaya, Parag; Wu, Daniel; Chang, Ken

doi:10.1109/jssc.2013.2274824

Cited by 14 publications

(5 citation statements)

References 16 publications

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“…Then, the input-referred noise is obtained by dividing (1) with the trans-impedance gain R as: Nowadays, in order to take advantage of the CMOS inverter in modern process technology, there has been a lot of approaches to adopt CMOS inverter into analog circuits. This paper focuses on the applications of high-speed analog circuits, and introduces three examples of that, amplifier in optical communication receivers [6,[14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30], high-speed clock and data buffer [13,[31][32][33][34][35][36][37][38][39][40][41], and output driver for high-speed I/O transmitter [13,40,[42][43][44][45][46][47][48][49][50].…”

Section: Cmos Inverter As An Amplifiermentioning

confidence: 99%

“…On the other hand, an AC-coupling capacitor is widely used at the input of the resistive feedback inverter, for clock buffer application [32][33][34][35][36][37][38][39] (Figure 10). The primary motivations of the AC coupling for the clock buffer are as follows:…”

Section: High Speed Buffermentioning

confidence: 99%

“…The last example is the output driver for high-speed I/O link. On the right side of Figure 12, we can find a conceptual diagram of a source-series terminated (SST) driver, which is also known as a voltage-mode driver [35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50]. Instead of relying on a parallel resistance to match the driver's output impedance with the characteristic impedance of the transmission channel, the SST driver adopts series termination.…”

Section: Output Driver For High-speed Wireline Communicationmentioning

confidence: 99%

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CMOS Inverter as Analog Circuit: An Overview

Bae

2019

JLPEA

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Since the CMOS technology scaling has focused on improving digital circuit, the design of conventional analog circuits has become more and more difficult. To overcome this challenge, there have been a lot of efforts to replace conventional analog circuits with digital implementations. Among those approaches, this paper gives an overview of the latest achievement on utilizing a CMOS inverter as an analog circuit. Analog designers have found that a simple resistive feedback pulls a CMOS inverter into an optimum biasing for analog operation. Recently developed applications of the resistive-feedback inverter, including CMOS inverter as amplifier, high-speed buffer, and output driver for high-speed link, are introduced and discussed in this paper.

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Section: Cmos Inverter As An Amplifiermentioning

confidence: 99%

Section: High Speed Buffermentioning

confidence: 99%

Section: Output Driver For High-speed Wireline Communicationmentioning

confidence: 99%

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CMOS Inverter as Analog Circuit: An Overview

Bae

2019

JLPEA

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“…By minimizing the mean square error (MSE), the signsign least-mean-square (SS-LMS) algorithm adjusts the coefficients of filters [1]- [4]. Adaptation loop by SS-LMS algorithm is done either in voltage domain or time domain.…”

Section: Introductionmentioning

confidence: 99%

Eye-open monitor using two-dimensional counter value profile

Son

Moon

Baek

et al. 2019

IEICE Electron. Express

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A simple eye-opening monitor (EOM) system based on two dimensional (2-D) counter-value profile is designed. The proposed EOM can be applied to adaptive equalizer coefficient control for better bit error rate (BER) performance in the high-speed serial interface. Input data is sampled 2048 times with 32 different clock phases on 32 different decision threshold amplitudes to the clocked comparator and the sampled outputs of '1' or '0' are recorded in the designated counter.The counter values at each phase and decision threshold amplitude are compared with a reference of 1024 for eye-opening monitor. The estimated eye-diagram is displayed on the monitor. Through the estimated eye-diagram, the optimal sampling timing can also be determined. The chip for sampling data and gathering the counter value has been designed through 180-nm CMOS process and 86 mW including I/O block is consumed on 2 Gb/s data rate.

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“…Ring oscillator has been widely adopted in a broad range of electrical applications [1][2][3] for its design simplicity, wide tuning range, low power and ease of integration. At the cost of a DC current, the CML-based differential ring oscillator, which is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

The Oscillation Frequency of CML-based Multipath Ring Oscillators

Song

Kim²,

Xiong³

2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-A novel phase interpolator (PI) based linear model of multipath ring oscillator (MPRO) is described in this paper. By modeling each delay cell as an ideal summer followed by a single pole RC filter, the oscillation frequency is derived for a 4-stage differential MPRO. It is analytically proved that the oscillation frequency increases with the growth of the forwarding factor α, which is also confirmed quantitatively through simulation. Based on the proposed model, it is shown that the power to frequency ratio keeps constant as the speed increases. Running at the same speed, a 4-stage MPRO can outperform the corresponding single-stage ring oscillator (SPRO) with 27% power saving, making MPRO with a large forwarding factor α an attractive option for lower power applications.

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A Low-Power 0.5–6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs

Cited by 14 publications

References 16 publications

CMOS Inverter as Analog Circuit: An Overview

CMOS Inverter as Analog Circuit: An Overview

Eye-open monitor using two-dimensional counter value profile

The Oscillation Frequency of CML-based Multipath Ring Oscillators

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