This paper presents an architecture for disparity estimation in real time which is designed to be used in a blind navigation assistance system. A highly pipelined hardware prototype has been designed and verified. Sum of Absolute Difference (SAD) algorithm is chosen as the cost function in the proposed architecture. The major design consideration is efficient hardware utilization and high throughput. This system is designed to support video resolutions upto 2048 x 2048 at high frame rates. The performance evaluation shows very low latency even at low processing frequency.
In this paper we employed Winner Take All (WTA) circuit for sensing the bit line capacitance. It is an important block in hardware realization of neural networks. The property of a neural logic of selection of the highest intensity signal amongst competing signals highly fits for our design of amplifying the voltage difference between bit lines quickly. A comparative study is done to show the better performance of our proposed design compared to the conventional cross-coupled amplifier. The design and simulation is carried out in Cadence virtuoso platform with UMC 0.18 m process technology.
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