This paper describes a novel Packet Triggered Architecture (PTA). This architecture takes advantage of programmable pipeline and parallel processing, which lead to MIMD (Multiple Instruction Multiple Data) architecture. The PTA is composed of two main blocks. The first block is constituted from Functional Units (FUs) and their interconnection network. The instructions in the PTA are composed of instruction packets. Every packet encapsulates a data and route across internal NoC (Network on Chip) to which enables dynamic data flow scheduling. This approach brings a new way of programming, because the programming is done by specifying FUs addresses and functions ports. Using of such a design allows create target hardware like a software application. The main advantages of this approach are that any processor can be emulated in the PTA, its ISA can be extended and special accelerators can be added too. Small loops are created directly inside the PTA and small concurrent Finite State Automats (FSM) can be created inside the PTA. The PTA can be as well used like an abstraction layer to easily design and create special-purpose hardware. There are some advantages in hardware design as well. The PTA does not need any complex instruction decoder. Instructions packets can be only fetched and dispatched to PTA. The PTA as well does not need any complex forwarding logic. The PTA can work as a system with improved reliability as well.
This article describes a basic algorithm for a division operation. Its performance and consideration of the implementation in VHDL are discussed. There are described three possible implementations, the maximum performance in FPGAs, e.g. propagation delays and number of necessary steps to enumerate the correct result. In the conclusion the performance and necessary number of steps are compared.
The article introduces the Multiplatform Library Configuration and Tuning Tool (MLCTT) system idea. Today there are many complex projects with digital hardware, where fast speed, low development cost and low power consumption are required. We hope that presented idea can be a good solution for this problem. The introduced MLCTT system is combination of Multiprocessor System on Chip and Multi Core System on Chip. It consists of rich set of functional blocks, which are part of almost all modern digital processing systems and defines some basic principles for easy connectivity between those blocks and external environment. By using this solution, the developers can easily create necessarily hardware for target application and easily change it during software development, if necessarily. The main advantage of this solution is independence on used processor(s) and easy network on chip scalability. The whole system is based on the SystemC TLM-2.0 model, because those features are suitable for software profiling and dynamic system generation. This allows the best performance and power consumption tuning for a desired application. The basic of this concept and its advantages are introduced in the paper.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.