Abstract:This paper describes a novel Packet Triggered Architecture (PTA). This architecture takes advantage of programmable pipeline and parallel processing, which lead to MIMD (Multiple Instruction Multiple Data) architecture. The PTA is composed of two main blocks. The first block is constituted from Functional Units (FUs) and their interconnection network. The instructions in the PTA are composed of instruction packets. Every packet encapsulates a data and route across internal NoC (Network on Chip) to which enable… Show more
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