We propose a structured design methodology to construct FSM-based programmable memory BIST. The proposed BIST can be programmed on-line, with a "macro command", to select a test algorithm from a predetermined set of algorithms that are built in the memory BIST. In general, there are a variety of heterogeneous memory modules in SOC, and it is not possible to test all of them with a single algorithm. Thus, the proposed scheme greatly simplifies the testing process. Besides, the proposed is more efficient in terms of circuit size and test data to be applied, and it requires less time to configure the BIST. We also develop a programmable memory BIST generator that automatically produces RTL model of the proposed BIST architecture for a given set of test algorithms. Experimental results show that the proposed method achieves a good flexibility with smaller circuit size compared with previous methods.
A low complexity baseband transceiver design for power line communication is presented. The proposed baseband transceiver adopts an M-ary Bi-Orthogonal Keying (MBOK) based Direct-Sequence Spread Spectrum (DSSS) modulation scheme. The front end signal is further modulated by a FSK scheme to combat serious channel impairments in power line network. No A/D or D/A converters are required and a simple dual-phase sampling technique is employed for timing recovery.Occupying a bandwidth of 400 kHz, the design has a 200 kHz chip rate and is capable of supporting a reliable 100 kbps data rate. The BER can be lower than 10 -3 when the SNR value reaches 20dB. The FPGA implementation results indicate the baseband kernel design consumes less than 3,000 logic gates and features a low circuit complexity and protocol robust solution.
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