Synchronization with the utility voltage is naturally carried out by a diode bridge stage in single phase active rectifiers, while an active synchronization is included in the control algorithms applied to modern bridgeless topologies. Sensorless line current rebuilding algorithms also need synchronization with the line voltage to compensate at least for part of the current estimation error. The PLL circuits employed in single phase AC-DC converters are reviewed and a new digital PLL algorithm, based on the synchronous reference frame, is proposed. It is implemented in a Field Programmable Gate Array (FPGA) to utilize the parallelism and superior time resolution. Considering a restricted frequency variation of the line voltage around the central frequency, the orthogonal signal is obtained by a discrete differential operator designed to ensure unity gain at the central frequency. Its performance, including the memory and computational cost, versus previously consolidated algorithms implemented in the same device is analyzed. Simulations and experimental results prove its suitable behavior in steady-state at different line frequencies and under line voltage and frequency transients.

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New power factor correction (PFC) stages such as bridgeless converters and the associated current shaping techniques require grid synchronization to ensure unity Displacement Power Factor (DPF). Sensorless line current rebuilding algorithms also need synchronization with the line voltage to compensate at least for part of the current estimation error. The application of a secondary control path to reach faster and more robustly the proper operation point previously applied in single/three-phase PLLs in grid connected converters is here proposed for the current sensorless bridgeless PFCs. This work analyzes the performance of three single-phase T/4 PLL structures, first without secondary control path, and later with feedforward and feedback secondary control paths, both in simulation and experimentally, and evaluates their applicability to current sensorless digitally controlled single phase bridgeless PFCs based on the current rebuilding technique.

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Single-phase Bridgeless power factor correction converters (PFCs) improve the conversion efficiency in comparison with the conventional PFCs, where a diode bridge plus a DC/DC boost converter are used, due to the absence of the input rectifier, but current sensing complexity increases. Its efficiency can be further increased, and its cost reduced by avoiding the input current sensor. This paper proposes a control strategy applicable to Bridgeless PFCs, implemented in a digital device (Field Programmable Gate Array, FPGA), where the grid current is not sensed. To compensate for the effect of the non-ideal operation of the converter, which result in current control errors, a third harmonic dependent function is introduced. The converter model is presented. Simulation and experimental results are used to assess the performance of the proposed method.

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