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Abstract-A new digital control technique for power factor correction is presented. The main novelty of the method is that there is no current sensor. Instead, the input current is digitally rebuilt, using the estimated input current for the current loop. Apart from that, the ADCs used for the acquisition of the input and output voltages have been designed ad-hoc. Taking advantage of the slow dynamic behavior of these voltages, almost completely digital ADCs have been designed, leaving only a comparator and an RC filter in the analog part. The final objective is obtaining a low cost digital controller which can be easily integrated in an ASIC along with the controller of paralleled and subsequent power sections.

Synchronization with the utility voltage is naturally carried out by a diode bridge stage in single phase active rectifiers, while an active synchronization is included in the control algorithms applied to modern bridgeless topologies. Sensorless line current rebuilding algorithms also need synchronization with the line voltage to compensate at least for part of the current estimation error. The PLL circuits employed in single phase AC-DC converters are reviewed and a new digital PLL algorithm, based on the synchronous reference frame, is proposed. It is implemented in a Field Programmable Gate Array (FPGA) to utilize the parallelism and superior time resolution. Considering a restricted frequency variation of the line voltage around the central frequency, the orthogonal signal is obtained by a discrete differential operator designed to ensure unity gain at the central frequency. Its performance, including the memory and computational cost, versus previously consolidated algorithms implemented in the same device is analyzed. Simulations and experimental results prove its suitable behavior in steady-state at different line frequencies and under line voltage and frequency transients.

The proliferation of non-linear loads and the increasing penetration of Distributed Energy Resources (DER) in Medium-Voltage (MV) and Low-Voltage (LV) distribution grids, make it more difficult to maintain the power quality levels in residential electrical grids, especially in the case of weak grids. Most household appliances contain a conventional Power Factor Corrector (PFC) rectifier, which maximizes the load Power Factor (PF) but does not contribute to the regulation of the voltage Total Harmonic Distortion (T HDV) in residential electrical grids. This manuscript proposes a modification for PFC controllers by adapting the operation mode depending on the measured T HDV. As a result, the PFCs operate either in a low current Total Harmonic Distortion (T HDI) mode or in the conventional resistor emulator mode and contribute to the regulation of the T HDV and the P F at the distribution feeders. To prove the concept, the modification is applied to a current sensorless Non-Linear Controller (NLC) applied to a single-phase Boost rectifier. Experimental results show its performance in a PFC front-end stage operating in Continuous Conduction Mode (CCM) connected to the grid with different T HDV .

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Esta es la versión de autor de la comunicación de congreso publicada en: This is an author produced version of a paper published in: Abstract-A circuit that compensates the volt-seconds error across the inductor in current sensorless digital control for continuous conduction mode power factor correction (PFC) stage is presented. Low cost ad-hoc sigma-delta analog to digital converters (ADCs) are used to sample the PFC input and output voltage. Instead of being measured, the input current is estimated in a digital circuit to be used in the current loop. A nonlinear carrier control is implemented in the digital controller in order to obtain the power factor correction. Drive signal's delays causes differences between the digital current and the real current, producing that volt-seconds error. The control algorithm is compensated taking into account the delays. The influence of a wrong compensation is presented. Experimental results show power factor values and harmonic content within the IEC 61000-3-2 Class C standard in different operation conditions. Furthermore, the use of this PFC stage for electronics ballast to compensate the effect of the utility voltage fluctuation in HID lamps is also verified taking advantage of the digital device capabilities.

Abstract-Traditional digital PFC (Power Factor Correction) uses three sensors to measure the input and output voltages and the input current. Each sensor, especially the input current one, increases the cost of the system and generates power losses in case of resistive sensors. This paper presents a controller for boost PFC converters. It uses pre-calculated duty cycles generated offline, and applies them to the switch. In order to control the converter with non-nominal conditions, just one ADC (Analog to Digital Converter) is used, which measures the output voltage. Measuring the average and the ripple of the output voltage with this ADC, the controller takes compensation action for changes in the input voltage but also in the load of the converter. The average value is used to control the input voltage changes, whilst the ripple value is used to control load changes. These two loops present low frequency bandwidth, so the ADC and the whole system can be low cost. Finally, a comparator is used to detect the zero-crossing of the input voltage, so the pre-calculated values are synchronized with the ac mains. In this way, the converter only uses one ADC and one comparator, both with low bandwidth. Results show that high power factor and normative compliance are reached, even under non-nominal conditions.