Neuromorphic computing based on spikes offers great potential in highly efficient computing paradigms. Recently, several hardware implementations of spiking neural networks based on traditional complementary metal-oxide semiconductor technology or memristors have been developed. However, an interface (called an afferent nerve in biology) with the environment, which converts the analog signal from sensors into spikes in spiking neural networks, is yet to be demonstrated. Here we propose and experimentally demonstrate an artificial spiking afferent nerve based on highly reliable NbOx Mott memristors for the first time. The spiking frequency of the afferent nerve is proportional to the stimuli intensity before encountering noxiously high stimuli, and then starts to reduce the spiking frequency at an inflection point. Using this afferent nerve, we further build a power-free spiking mechanoreceptor system with a passive piezoelectric device as the tactile sensor. The experimental results indicate that our afferent nerve is promising for constructing self-aware neurorobotics in the future.

Neural networks based on memristive devices [1][2][3] have shown potential in substantially improving throughput and energy efficiency for machine learning [4] and artificial intelligence [5], especially in edge applications. [6][7][8][9][10][11][12][13][14][15][16][17][18][19] Because training a neural network model from scratch is very costly, it is impractical to do it individually on billions of memristive neural networks distributed at the edge. A practical approach would be to download the synaptic weights obtained from the cloud training and program them directly into memristors for the commercialization of edge applications (Figure 1a). Some posttuning in memristor conductance to adapt local situations may follow afterward or during applications. Therefore, a critical requirement on memristors for neural network applications is a high-precision programming ability to guarantee uniform and accurate performance across a massive number of memristive networks. [20][21][22][23][24][25][26] That translates into the requirement of many distinguishable conductance levels on each memristive device, not just lab-made devices but more importantly, devices fabricated in foundries. High precision memristors also benefit other neural network applications, such as training and scientific computing. [23,27] Here we report over 2048 conductance levels, the largest number among all types of memories ever reported, achieved with memristors in fully integrated chips with 256 ´ 256 memristor arrays monolithically integrated on CMOS circuits in a standard foundry. We have unearthed the underlying physics that previously limited the number of achievable conductance levels in memristors and developed electrical operation protocols to circumvent such limitations. These results reveal insights into the fundamental understanding of the microscopic picture of memristive switching and provide approaches to enable high-precision memristors for various applications.Memristive switching devices are known for their relatively large dynamical range of conductance, which can potentially lead to a large number of discrete conductance levels. However, the highest number reported to date has been no more than two hundred. [20]

A fully hardware-based memristive neural network is capable of delivering high computing throughput and power efficiency.

Sneak path current is a fundamental issue and a major roadblock to the wide application of memristor crossbar arrays. Traditional selectors such as transistors compromise the 2D scalability and 3D stack‐ability of the array, while emerging selectors with highly nonlinear current–voltage relations contradict the requirement of a linear current–voltage relation for efficient multiplication by directly using Ohm's law. Herein, the concept of a timing selector is proposed and demonstrated, which addresses the sneak path issue with a voltage‐dependent delay time of its transient switching behavior, while preserving a linear current–voltage relationship for computation. Crossbar arrays with silver‐based diffusive memristors as the timing selectors are built and the operation principle and operational windows are experimentally demonstrated. The timing selector enables large memristor crossbar arrays that can be used to solve large‐dimension real‐world problems in machine intelligence and neuromorphic computing.

A diffusive memristor is a promising building block for brain‐inspired computing hardware. However, the randomness in the device relaxation dynamics limits the wide‐range adoption of diffusive memristors in large arrays. In this work, the device stack is engineered to achieve a much‐improved uniformity in the relaxation time (standard deviation σ reduced from ≈12 to ≈0.32 ms). The memristor is further connected with a resistor or a capacitor and the relaxation time is tuned between 1.13 µs and 1.25 ms, ranging from three orders of magnitude. The hierarchy of time surfaces (HOTS) algorithm, to utilize the tunable and uniform relaxation behavior for spike generation, is implemented. An accuracy of 77.3% is achieved in recognizing moving objects in the neuromorphic MNIST (N‐MNIST) dataset. The work paves the way for building emerging neuromorphic computing hardware systems with ultralow power consumption.

Implementing synaptic weights using tunable conductance of memristors offers significant power and computing throughput improvements through in-memory analog computing. Hardware-based perceptron implementation with memristor crossbar arrays has attracted increased interest in recent years. However, all the previous memristor-based perceptron demonstrations perform some critical operations such as the activation functions using software, leading to substantial back-and-forth communication between the perceptron and a computer. In this work, we show that by implementing the activation functions between different layers of a perceptron all on hardware, using only analog components, we can avoid those unnecessary communication and improve power efficiency and throughput. We have designed a compact multichannel rectified linear unit activation function and developed a two-layer perceptron using two individual memristor crossbar arrays. We have achieved a 93.63% recognition accuracy in classifying the Modified National Institute of Standards and Technology dataset using the analog neurons, comparable with that for a partially software counterpart, and a much improved power efficiency.

Timing Selector In article number http://doi.wiley.com/10.1002/smsc.202100072, Mingyi Rao, Zhongrui Wang, J. Joshua Yang, and co‐workers conceptualize and demonstrate a timing selector, which can utilize its nonlinear relation between switching time and voltage, instead of current and voltage in traditional selectors, to block sneaking current in memristive crossbar arrays. The operation principles are formulated together with experimental demos using integrated one‐selector‐one‐memristor (1S1M) structures.

Neural networks based on memristive devices have shown potential in substantially improving throughput and energy efficiency for machine learning and artificial intelligence, especially in edge applications. Because training a neural network model from scratch is very costly, it is impractical to do it individually on billions of memristive neural networks distributed at the edge. A practical approach would be to download the synaptic weights obtained from the cloud training and program them directly into memristors for the commercialization of edge applications. Some post-tuning in memristor conductance may follow afterward or during applications. Therefore, a critical requirement on memristors for neural network applications is a high-precision programming ability to guarantee uniform and accurate performance across a massive number of memristive networks. This translates into the requirement of many distinguishable conductance levels on each memristive device, not just lab-made devices but more importantly, devices fabricated in foundries. High precision memristors also benefit other neural network applications, such as training and scientific computing. Here we report over 2048 conductance levels, the largest number among all types of memories ever reported, achieved with memristors in fully integrated chips with 256x256 memristor arrays monolithically integrated on CMOS circuits in a standard foundry. We have unearthed the underlying physics that previously limited the number of achievable conductance levels in memristors and developed electrical operation protocols to circumvent such limitations. These results reveal insights into the fundamental understanding of the microscopic picture of memristive switching and provide approaches to enabling high-precision memristors for various applications.