2021 IEEE International Symposium on Circuits and Systems (ISCAS) 2021
DOI: 10.1109/iscas51556.2021.9401793
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All Hardware-Based Two-Layer Perceptron Implemented in Memristor Crossbar Arrays

Abstract: Implementing synaptic weights using tunable conductance of memristors offers significant power and computing throughput improvements through in-memory analog computing. Hardware-based perceptron implementation with memristor crossbar arrays has attracted increased interest in recent years. However, all the previous memristor-based perceptron demonstrations perform some critical operations such as the activation functions using software, leading to substantial back-and-forth communication between the perceptron… Show more

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“…An increase in source and detector efficiencies [46] could further reduce the energy consumption by an order of magnitude to the single-femtojoule per MAC regime. DAC and ADC costs may also be eliminated with analog electronic nonlinearities [22,58], as analog output activations from one layer can be directly used as inputs to the next layer. The inputs to the first layer may also be in the analog domain, e.g., as they are read out from a sensor.…”
Section: Discussionmentioning
confidence: 99%
“…An increase in source and detector efficiencies [46] could further reduce the energy consumption by an order of magnitude to the single-femtojoule per MAC regime. DAC and ADC costs may also be eliminated with analog electronic nonlinearities [22,58], as analog output activations from one layer can be directly used as inputs to the next layer. The inputs to the first layer may also be in the analog domain, e.g., as they are read out from a sensor.…”
Section: Discussionmentioning
confidence: 99%