The Soft-Error Rate (SER) estimation is used to predict how electronic systems will respond to the transient electrical pulses induced by the ionizing radiation. SER estimation by radiation test is an accurate method, but it is expensive and requires the real device. Traditional simulation methods incorporate logical, temporal and electrical masking effects while injecting faults at the output of the device's functional elements. Nevertheless, they do not consider the probability of the ionizing radiation to produce a transient fault at the output of each class of functional element. On the other hand, studies in the stochastic computing domain deal with a probabilistic faultinjection approach. Since many concomitant faults among the elements may occur, the fault probability of each element is treated independently. This leads to the use of one Pseudo-Random Number Generator (PRNG) and a probability comparator for each functional element. However, the analysis of a single fault is usually enough for SER estimation. In this context, this work presents a different approach for probability-aware faultinjection, in which a weighted distribution of faults is defined considering the relative fault probability of each functional element. This approach enables the use of just one PRNG and a decoder for the entire device, instead of a pair 'PRNGcomparator' per element, leading to a significant reduction in logic blocks consumption. For the example analyzed in this study, the use of relative fault probability decreases the number of logic blocks from 875 (adopting independent fault probability) to 495.
The application of an electrical pulse to emulate a Single Event Transient (SET) is a strategy adopted in the study of pulse broadening and quenching effects. This strategy is usually restricted to the combinational circuits due to the temporal masking effect of the clock used in sequential circuits. Emulationbased fault-injection approaches, which consider the SET in addition to the SEU (Single Event Upset), do not use electrical pulses to emulate the SETs. Despite all these restrictions, an emulation-based fault-injection approach for Soft-Error Rate (SER) estimation, running on the same device chosen as the final target, is suitable for real electrical pulses for SET emulation. As the SER has a statistical nature, the fault-injection method does not need to control when the SET occurs inside the clock cycle. Instead, it needs to guarantee that the SET may occur at any moment, without bias. On the other hand, once using the same device, the concern about electrical distortion is restricted to the fault-injection process itself. In this context, this work presents an analysis of the use of an FPGA self-produced transient pulse as an emulated SET for SER estimation. The results show that is feasible to adopt this approach in some particular cases, with advantages related to the estimation process speed.
Soft-Error Vulnerability (SEV) is a parameter used to evaluate the robustness of a circuit to the induced Soft Errors (SEs). There are many techniques for SEV estimation, including analytical, electrical and logic simulations, and emulation-based approaches. Each of them has advantages and disadvantages regarding estimation time, resources consumption, accuracy, and restrictions over the analysed circuit. Concerning the ionising radiation effects, some analytical and electrical simulation approaches take into account how the circuit topology and the applied input patterns affect their susceptibilities to Single Event Transient (SET) at the gate level. On the other hand, logic simulation and emulation techniques usually ignore these SET susceptibilities. In this context, we propose a logic simulation-based probability-aware approach for SEV estimation that takes into account the specific SET susceptibility of each circuit gate. For a given operational scenario, we extract the input patterns applied to each gate and calculate its specific SET susceptibility. For the 38 analysed benchmark circuits, we obtained a reduction from 15.27% to 0.68% in the average SEV estimation error, when comparing the estimated value to a reference obtained at the transistor level. The results point out an improvement of the SEV estimation process by considering the specific SET susceptibilities.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.