Impact evaluation of logic blocks configuration on FPGA's soft error rate estimation

Armelin, Fabio B.; Naviner, Lírida Alves de Barros; d’Amore, Roberto; Azevedo, Irany A.

doi:10.1109/icecs.2016.7841186

Cited by 4 publications

(5 citation statements)

References 12 publications

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“…The higher soft-error susceptibility of the CUT when adopting a weighted distribution of faults is consistent with the values observed in [5]. However, it is specific to this CUT.…”

Section: Discussionsupporting

confidence: 86%

“…The circuit under test is an 8-bit counter analyzed in a previous study [5]. This circuit has an 8-bit output, and a clock and a reset inputs.…”

Section: E Circuit Under Testmentioning

confidence: 99%

“…Its synthesis in the target device resulted in 35 logic blocks (1 AND2, 6 AND3, 6 AOI1B, 8 DFN1C1, 1 INV, 1 NOR2A, 3 NOR2B, 1 NOR3B, 1 NOR3C, and 7 XOR2). The probabilities reported in [5] were adopted in this work and used for determining the weighted fault distribution (Table I).…”

Section: E Circuit Under Testmentioning

confidence: 99%

“…In these devices, the same logic block can be configured for many distinct functions. In fact, a previous study analyzed how the logic block configuration may affect the SER estimation for an FPGA [5].…”

Section: Introductionmentioning

confidence: 99%

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Probability aware fault-injection approach for SER estimation

Armelin

Naviner

d’Amore

2018

2018 IEEE 19th Latin-American Test Symposium (LATS)

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The Soft-Error Rate (SER) estimation is used to predict how electronic systems will respond to the transient electrical pulses induced by the ionizing radiation. SER estimation by radiation test is an accurate method, but it is expensive and requires the real device. Traditional simulation methods incorporate logical, temporal and electrical masking effects while injecting faults at the output of the device's functional elements. Nevertheless, they do not consider the probability of the ionizing radiation to produce a transient fault at the output of each class of functional element. On the other hand, studies in the stochastic computing domain deal with a probabilistic faultinjection approach. Since many concomitant faults among the elements may occur, the fault probability of each element is treated independently. This leads to the use of one Pseudo-Random Number Generator (PRNG) and a probability comparator for each functional element. However, the analysis of a single fault is usually enough for SER estimation. In this context, this work presents a different approach for probability-aware faultinjection, in which a weighted distribution of faults is defined considering the relative fault probability of each functional element. This approach enables the use of just one PRNG and a decoder for the entire device, instead of a pair 'PRNGcomparator' per element, leading to a significant reduction in logic blocks consumption. For the example analyzed in this study, the use of relative fault probability decreases the number of logic blocks from 875 (adopting independent fault probability) to 495.

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“…The higher soft-error susceptibility of the CUT when adopting a weighted distribution of faults is consistent with the values observed in [5]. However, it is specific to this CUT.…”

Section: Discussionsupporting

confidence: 86%

“…The circuit under test is an 8-bit counter analyzed in a previous study [5]. This circuit has an 8-bit output, and a clock and a reset inputs.…”

Section: E Circuit Under Testmentioning

confidence: 99%

Section: E Circuit Under Testmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Probability aware fault-injection approach for SER estimation

Armelin

Naviner

d’Amore

2018

2018 IEEE 19th Latin-American Test Symposium (LATS)

Self Cite

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“…A preliminary version of this study was presented in [18], in which we analysed the impact of the CLB configuration (topology) on the circuit's SEV. That preliminary analysis was performed for two small circuits and limited to the CLB configurations used by these circuits.…”

Section: Introductionmentioning

confidence: 99%

Soft-Error Vulnerability Estimation Approach Based on the SET Susceptibility of Each Gate

2019

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Soft-Error Vulnerability (SEV) is a parameter used to evaluate the robustness of a circuit to the induced Soft Errors (SEs). There are many techniques for SEV estimation, including analytical, electrical and logic simulations, and emulation-based approaches. Each of them has advantages and disadvantages regarding estimation time, resources consumption, accuracy, and restrictions over the analysed circuit. Concerning the ionising radiation effects, some analytical and electrical simulation approaches take into account how the circuit topology and the applied input patterns affect their susceptibilities to Single Event Transient (SET) at the gate level. On the other hand, logic simulation and emulation techniques usually ignore these SET susceptibilities. In this context, we propose a logic simulation-based probability-aware approach for SEV estimation that takes into account the specific SET susceptibility of each circuit gate. For a given operational scenario, we extract the input patterns applied to each gate and calculate its specific SET susceptibility. For the 38 analysed benchmark circuits, we obtained a reduction from 15.27% to 0.68% in the average SEV estimation error, when comparing the estimated value to a reference obtained at the transistor level. The results point out an improvement of the SEV estimation process by considering the specific SET susceptibilities.

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FPGA hardware accelerator for holographic memory calculations for optically reconfigure gate arrays

Ito

Watanabe

2017

2017 IEEE International Conference on Space Optical Systems and Applications (ICSOS)

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Impact evaluation of logic blocks configuration on FPGA's soft error rate estimation

Cited by 4 publications

References 12 publications

Probability aware fault-injection approach for SER estimation

Probability aware fault-injection approach for SER estimation

Soft-Error Vulnerability Estimation Approach Based on the SET Susceptibility of Each Gate

FPGA hardware accelerator for holographic memory calculations for optically reconfigure gate arrays

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